{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,8,15]],"date-time":"2023-08-15T08:41:08Z","timestamp":1692088868038},"reference-count":22,"publisher":"World Scientific Pub Co Pte Ltd","issue":"13","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2023,9,15]]},"abstract":" Custom computing architectures on field programmable gate array (FPGA) platforms are a viable solution to further accelerate convolutional neural network (CNN) inference. However, due to the large size feature map matrix data, the optimization of CNN feature maps storage computing on FPGA remains a challenge. To overcome these challenges, a FPGA-oriented memory access optimization method for CNN is proposed. Firstly, the feature map partition strategy is used to group the feature map efficiently. Second, the input and the output caching rotation methods are employed in adaptive memory access mode. Third, a caching hybrid rotation method is proposed to optimize memory access performance and can effectively reduce the access time of the CNN feature map. Experimental results based on SkyNet and VGG16 show that the inference speed of the proposed model is accelerated by 7.1 times compared with the previous conventional memory access optimization for CNN on FPGA. Through the evaluation of computational energy efficiency, our method can be improved by 6.4 times compared to the current typical accelerators. <\/jats:p>","DOI":"10.1142\/s0218126623502183","type":"journal-article","created":{"date-parts":[[2023,1,19]],"date-time":"2023-01-19T06:58:36Z","timestamp":1674111516000},"source":"Crossref","is-referenced-by-count":0,"title":["Caching Hybrid Rotation: A Memory Access Optimization Method for CNN on FPGA"],"prefix":"10.1142","volume":"32","author":[{"given":"Dong","family":"Dong","sequence":"first","affiliation":[{"name":"Beijing Key Laboratory of Digital Media, State Key Lab Virtual Real Technology & Systems, Beihang University, Beijing 100191, China"}]},{"given":"Hongxu","family":"Jiang","sequence":"additional","affiliation":[{"name":"Beijing Key Laboratory of Digital Media, State Key Lab Virtual Real Technology & Systems, Beihang University, Beijing 100191, China"}]},{"ORCID":"http:\/\/orcid.org\/0000-0002-3761-1759","authenticated-orcid":false,"given":"Xuekai","family":"Wei","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Internet of Things for Smart City, and Department of Electrical and Computer Engineering, University of Macau, Macao, 999078, China"}]}],"member":"219","published-online":{"date-parts":[[2023,3,4]]},"reference":[{"key":"S0218126623502183BIB001","doi-asserted-by":"crossref","first-page":"3772","DOI":"10.1109\/TPDS.2022.3170305","volume":"33","author":"Wang T.","year":"2022","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"S0218126623502183BIB002","author":"Zhang M.","year":"2022","journal-title":"IEEE Trans. Autom. Sci. Eng."},{"issue":"2","key":"S0218126623502183BIB003","doi-asserted-by":"crossref","first-page":"925","DOI":"10.1109\/TCC.2020.2992461","volume":"10","author":"Cong P.","year":"2020","journal-title":"IEEE Trans. Cloud Comput."},{"key":"S0218126623502183BIB004","doi-asserted-by":"crossref","first-page":"4567","DOI":"10.1093\/bioinformatics\/btab687","volume":"37","author":"Valentin J.","year":"2021","journal-title":"Bioinformatics"},{"key":"S0218126623502183BIB005","doi-asserted-by":"crossref","first-page":"2250017","DOI":"10.1142\/S0219467822500176","volume":"22","author":"Vaidya B.","year":"2022","journal-title":"Int. J. Image Graph."},{"key":"S0218126623502183BIB006","doi-asserted-by":"crossref","first-page":"6215","DOI":"10.1038\/s41598-021-85652-1","volume":"11","author":"Sohail A.","year":"2021","journal-title":"Sci. Rep."},{"key":"S0218126623502183BIB007","doi-asserted-by":"crossref","first-page":"2250134","DOI":"10.1142\/S0218126622501341","volume":"31","author":"Huang W.","year":"2022","journal-title":"J. Circuits Syst. Comput."},{"key":"S0218126623502183BIB008","doi-asserted-by":"crossref","first-page":"2230005","DOI":"10.1142\/S0218126622300057","volume":"31","author":"Yang P.","year":"2022","journal-title":"J. Circuits Syst. Comput."},{"key":"S0218126623502183BIB009","doi-asserted-by":"crossref","first-page":"2250127","DOI":"10.1142\/S0218126622501274","volume":"31","author":"Gu F.","year":"2022","journal-title":"J. Circuits Syst. Comput."},{"key":"S0218126623502183BIB011","first-page":"1324","volume":"12","author":"Assad F.","year":"2022","journal-title":"Int. J. Electr. Comput. Eng."},{"key":"S0218126623502183BIB012","doi-asserted-by":"crossref","first-page":"2250126","DOI":"10.1142\/S0218126622501262","volume":"31","author":"Gou F.","year":"2022","journal-title":"J. Circuits Syst. Comput."},{"key":"S0218126623502183BIB013","first-page":"6848","volume-title":"Proc. IEEE Conf. Computer Vision and Pattern Recognition","author":"Zhang X."},{"key":"S0218126623502183BIB014","first-page":"269","volume-title":"Int. Conf. Architectural Support for Programming Languages & Operating Systems","author":"Chen T."},{"key":"S0218126623502183BIB015","first-page":"26","volume-title":"Proc. 2016 ACM\/SIGDA Int. Symp.","author":"Qiu J.","year":"2016"},{"key":"S0218126623502183BIB016","first-page":"1","volume-title":"Proc. 54th Annual Design Automation Conference.","author":"Wei X.","year":"2017"},{"key":"S0218126623502183BIB017","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3140659.3080246","volume":"45","author":"Jouppi N. P.","year":"2017","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"S0218126623502183BIB018","first-page":"131","volume-title":"Brazilian Conf. Intelligent Systems","author":"Carvalho E. F."},{"key":"S0218126623502183BIB019","first-page":"216","volume":"2","author":"Zhang X.","year":"2020","journal-title":"Proc. Mach. Learn. Syst."},{"key":"S0218126623502183BIB020","first-page":"1","author":"Simonyan K.","year":"2014","journal-title":"Comput. Sci."},{"key":"S0218126623502183BIB021","first-page":"1","volume-title":"Design Automation Conf.","author":"Xiao Q.","year":"2017"},{"key":"S0218126623502183BIB022","first-page":"784","author":"Mei C.","year":"2018","journal-title":"Signal Inf. Process."},{"key":"S0218126623502183BIB023","doi-asserted-by":"crossref","first-page":"1874","DOI":"10.1109\/TVLSI.2019.2913958","volume":"27","author":"Lian X.","year":"2019","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126623502183","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,15]],"date-time":"2023-08-15T08:22:39Z","timestamp":1692087759000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/10.1142\/S0218126623502183"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3,4]]},"references-count":22,"journal-issue":{"issue":"13","published-print":{"date-parts":[[2023,9,15]]}},"alternative-id":["10.1142\/S0218126623502183"],"URL":"https:\/\/doi.org\/10.1142\/s0218126623502183","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,3,4]]}}}