{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:37:58Z","timestamp":1740116278948,"version":"3.37.3"},"reference-count":12,"publisher":"World Scientific Pub Co Pte Ltd","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,11]]},"abstract":" In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2\u2019s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2\u2019s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2\u2019s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results. <\/jats:p>","DOI":"10.1142\/s0218126618501840","type":"journal-article","created":{"date-parts":[[2018,2,14]],"date-time":"2018-02-14T22:24:21Z","timestamp":1518647061000},"page":"1850184","source":"Crossref","is-referenced-by-count":16,"title":["Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2\u2019s Complement Code Converter"],"prefix":"10.1142","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8305-4818","authenticated-orcid":false,"given":"Heranmoy","family":"Maity","sequence":"first","affiliation":[{"name":"Department of ECE, NSHM Knowledge Campus, Durgapur, West Bengal 713212, India"}]},{"given":"Arijit Kumar","family":"Barik","sequence":"additional","affiliation":[{"name":"Department of ECE, Birbhum Institute of Engineering and Technology, Suri, West Bengal 731101, India"}]},{"given":"Arindam","family":"Biswas","sequence":"additional","affiliation":[{"name":"Department of ECE, Asansol Engineering College, Asansol, West Bengal 713305, India"}]},{"given":"Anup Kumar","family":"Bhattacharjee","sequence":"additional","affiliation":[{"name":"Department of ECE, National Institute of Technology Durgapur, Durgapur, West Bengal 713209, India"}]},{"given":"Anita","family":"Pal","sequence":"additional","affiliation":[{"name":"Department of Mathematics, National Institute of Technology Durgapur, Durgapur, West Bengal 713209, India"}]}],"member":"219","published-online":{"date-parts":[[2018,6,22]]},"reference":[{"key":"S0218126618501840BIB001","doi-asserted-by":"publisher","DOI":"10.1142\/S0219749916500192"},{"key":"S0218126618501840BIB002","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811448"},{"key":"S0218126618501840BIB003","doi-asserted-by":"publisher","DOI":"10.1147\/rd.176.0525"},{"key":"S0218126618501840BIB004","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126609005083"},{"key":"S0218126618501840BIB005","doi-asserted-by":"publisher","DOI":"10.1142\/S0219749911007447"},{"key":"S0218126618501840BIB006","doi-asserted-by":"publisher","DOI":"10.1364\/ON.11.2.000011"},{"key":"S0218126618501840BIB007","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.32.3266"},{"key":"S0218126618501840BIB008","doi-asserted-by":"publisher","DOI":"10.1145\/1877745.1877748"},{"key":"S0218126618501840BIB010","doi-asserted-by":"publisher","DOI":"10.1007\/BF01857727"},{"key":"S0218126618501840BIB011","doi-asserted-by":"publisher","DOI":"10.1007\/s10825-017-0960-4"},{"key":"S0218126618501840BIB012","first-page":"715","volume":"7","author":"Haghparast M.","year":"2011","journal-title":"Middle-East J. Sci. Res."},{"key":"S0218126618501840BIB015","first-page":"24","volume":"1","author":"Gandhi S. M.","year":"2014","journal-title":"Int. J. Inf. Technol. Mech. Eng."}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126618501840","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T01:05:32Z","timestamp":1565139932000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126618501840"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6,22]]},"references-count":12,"journal-issue":{"issue":"12","published-online":{"date-parts":[[2018,6,22]]},"published-print":{"date-parts":[[2018,11]]}},"alternative-id":["10.1142\/S0218126618501840"],"URL":"https:\/\/doi.org\/10.1142\/s0218126618501840","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"type":"print","value":"0218-1266"},{"type":"electronic","value":"1793-6454"}],"subject":[],"published":{"date-parts":[[2018,6,22]]}}}