{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,12,21]],"date-time":"2023-12-21T10:58:41Z","timestamp":1703156321315},"reference-count":30,"publisher":"World Scientific Pub Co Pte Lt","issue":"06","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,6,15]]},"abstract":" An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS.\u00a0SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit. <\/jats:p>","DOI":"10.1142\/s0218126618500925","type":"journal-article","created":{"date-parts":[[2017,10,11]],"date-time":"2017-10-11T07:52:12Z","timestamp":1507708332000},"page":"1850092","source":"Crossref","is-referenced-by-count":3,"title":["Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration"],"prefix":"10.1142","volume":"27","author":[{"given":"Prateek","family":"Jain","sequence":"first","affiliation":[{"name":"ECED MNIT, Jaipur (Raj.), India"}]},{"given":"Amit","family":"Joshi","sequence":"additional","affiliation":[{"name":"ECED MNIT, Jaipur (Raj.), India"}]}],"member":"219","published-online":{"date-parts":[[2018,2,22]]},"reference":[{"key":"S0218126618500925BIB003","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2173976"},{"key":"S0218126618500925BIB007","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-0686-6"},{"key":"S0218126618500925BIB008","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2011.2177267"},{"key":"S0218126618500925BIB009","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2014.954634"},{"key":"S0218126618500925BIB010","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2013.805391"},{"key":"S0218126618500925BIB011","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-7702-0"},{"key":"S0218126618500925BIB012","first-page":"1","volume":"3","author":"Mollazadeh M.","year":"2009","journal-title":"IEEE Trans. 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