{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T14:14:23Z","timestamp":1649168063640},"reference-count":4,"publisher":"World Scientific Pub Co Pte Lt","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,5]]},"abstract":" Scratch-Pad Memories (SPMs) have been increasingly used in real-time and embedded systems. However, it is still unknown and challenging to reduce the worst-case execution time (WCET) for hybrid SPM-cache architecture, where an SPM and a cache memory are placed on-chip in parallel to cooperatively improve performance and\/or energy efficiency. In this paper, we study four SPM allocation strategies to reduce the WCET for hybrid SPM-caches with different complexities. These algorithms differ by whether or not they can cooperate with the cache or be aware of the WCET. Our evaluation shows that the cache-aware and WCET-oriented SPM allocation can minimize the WCET for real-time benchmarks with little or even positive impact on the average-case execution time (ACET). <\/jats:p>","DOI":"10.1142\/s0218126618500809","type":"journal-article","created":{"date-parts":[[2017,9,25]],"date-time":"2017-09-25T06:07:38Z","timestamp":1506319658000},"page":"1850080","source":"Crossref","is-referenced-by-count":3,"title":["Cache-Aware SPM Allocation to Reduce Worst-Case Execution Time for Hybrid SPM-Caches"],"prefix":"10.1142","volume":"27","author":[{"given":"Lan","family":"Wu","sequence":"first","affiliation":[{"name":"Compiler, Architecture, and Realtime Systems (CARS) Lab, Virginia Commonwealth University, Richmond, VA 23284, USA"}]},{"ORCID":"http:\/\/orcid.org\/0000-0003-1343-2817","authenticated-orcid":false,"given":"Wei","family":"Zhang","sequence":"additional","affiliation":[{"name":"Compiler, Architecture, and Realtime Systems (CARS) Lab, Virginia Commonwealth University, Richmond, VA 23284, USA"}]}],"member":"219","published-online":{"date-parts":[[2018,2,6]]},"reference":[{"key":"S0218126618500809BIB010","doi-asserted-by":"publisher","DOI":"10.1145\/581888.581891"},{"key":"S0218126618500809BIB024","first-page":"52","author":"Alt M.","year":"1996","journal-title":"Proc. Third International Symposium on Static Analysis"},{"key":"S0218126618500809BIB025","doi-asserted-by":"publisher","DOI":"10.1017\/CCOL0521340446.006"},{"key":"S0218126618500809BIB029","doi-asserted-by":"publisher","DOI":"10.1109\/12.743411"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126618500809","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T19:49:39Z","timestamp":1565120979000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126618500809"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2,6]]},"references-count":4,"journal-issue":{"issue":"05","published-online":{"date-parts":[[2018,2,6]]},"published-print":{"date-parts":[[2018,5]]}},"alternative-id":["10.1142\/S0218126618500809"],"URL":"https:\/\/doi.org\/10.1142\/s0218126618500809","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,2,6]]}}}