{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T07:33:49Z","timestamp":1648884829805},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Parallel Process. Lett."],"published-print":{"date-parts":[[1997,12]]},"abstract":" Tiling has been used by parallelizing compilers to define fine-grain parallel tasks and to optimize cache performance. In this paper we present a novel compile-time technique, called miss-driven cache simulation, for determining loop tile sizes that achieve the highest cache hit-rate. The widening disparity between a processor's peak instruction rate and main memory access time in modern computer systems makes this kind of optimization increasingly important for overall program efficiency. <\/jats:p> Our simulation technique generates only those references of a loop nest that may generate a cache memory miss and processes them on an architecturally accurate cache model at compile-time. Processing only a small portion of the memory reference trace of a program yields simulation speeds in the millions of memory references per second on workstations, with statistics of misses per reference and inter-reference interference counts gathered at the same time. These simulation speeds and statistics allow for the accurate analysis of the impact of cache optimizations at compile-time. <\/jats:p> We discuss the results of applying this method to guide loop tiling for such commonly used computational kernels as matrix multiplication and Jacobi iteration for various cache parameters. <\/jats:p>","DOI":"10.1142\/s0129626497000395","type":"journal-article","created":{"date-parts":[[2003,10,6]],"date-time":"2003-10-06T11:00:00Z","timestamp":1065438000000},"page":"393-407","source":"Crossref","is-referenced-by-count":0,"title":["Compile-Time Cache Performance Prediction and Its Application to Tiling"],"prefix":"10.1142","volume":"07","author":[{"given":"Wesley K.","family":"Kaplow","sequence":"first","affiliation":[{"name":"Department of Computer Science, Rensselaer Polytechnic Institute, Troy, N.Y.\u00a012180-3590, USA"}]},{"given":"Boleslaw K.","family":"Szymanski","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Rensselaer Polytechnic Institute, Troy, N.Y.\u00a012180-3590, USA"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["Parallel Processing Letters"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0129626497000395","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T13:32:06Z","timestamp":1565184726000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0129626497000395"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,12]]},"references-count":0,"journal-issue":{"issue":"04","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1997,12]]}},"alternative-id":["10.1142\/S0129626497000395"],"URL":"https:\/\/doi.org\/10.1142\/s0129626497000395","relation":{},"ISSN":["0129-6264","1793-642X"],"issn-type":[{"value":"0129-6264","type":"print"},{"value":"1793-642X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1997,12]]}}}