{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,4]],"date-time":"2023-09-04T21:50:58Z","timestamp":1693864258151},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Parallel Process. Lett."],"published-print":{"date-parts":[[1997,12]]},"abstract":" Tiling is a technique used for exploiting medium-grain parallelism in nested loops. It relies on a first step that detects sets of permutable nested loops. All algorithms developed so far consider the statements of the loop body as a single block, in other words, they are not able to take advantage of the structure of dependences between different statements. In this paper, we overcame this limitation by showing how the structure of the reduced dependence graph can be taken into account for detecting more permutable loops. Our method combines graph retiming techniques and graph scheduling techniques. It can be viewed as an extension of Wolf and Lam's algorithm to the case of loops with multiple statements. Loan independent dependences play a particular role in our study, and we show how the way we handle them can be useful for fine-grain loop parallelization as well. <\/jats:p>","DOI":"10.1142\/s0129626497000383","type":"journal-article","created":{"date-parts":[[2003,10,6]],"date-time":"2003-10-06T11:00:00Z","timestamp":1065438000000},"page":"379-392","source":"Crossref","is-referenced-by-count":28,"title":["Combining Retiming and Scheduling Techniques for Loop Parallelization and Loop Tiling"],"prefix":"10.1142","volume":"07","author":[{"given":"Alain","family":"Darte","sequence":"first","affiliation":[{"name":"CNRS URA 1398, Ecole Normale Sup\u00e9rieure de Lyon, 69364 LYON Cedex 07, France"}]},{"given":"Georges-Andr\u00e9","family":"Silber","sequence":"additional","affiliation":[{"name":"CNRS URA 1398, Ecole Normale Sup\u00e9rieure de Lyon, 69364 LYON Cedex 07, France"}]},{"given":"Fr\u00e9d\u00e9ric","family":"Vivien","sequence":"additional","affiliation":[{"name":"CNRS URA 1398, Ecole Normale Sup\u00e9rieure de Lyon, 69364 LYON Cedex 07, France"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["Parallel Processing Letters"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0129626497000383","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T13:32:06Z","timestamp":1565184726000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0129626497000383"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,12]]},"references-count":0,"journal-issue":{"issue":"04","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1997,12]]}},"alternative-id":["10.1142\/S0129626497000383"],"URL":"https:\/\/doi.org\/10.1142\/s0129626497000383","relation":{},"ISSN":["0129-6264","1793-642X"],"issn-type":[{"value":"0129-6264","type":"print"},{"value":"1793-642X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1997,12]]}}}