{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T23:58:51Z","timestamp":1729641531676,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1109\/vts.2011.5783730","type":"proceedings-article","created":{"date-parts":[[2011,6,7]],"date-time":"2011-06-07T20:35:25Z","timestamp":1307478925000},"page":"254-259","source":"Crossref","is-referenced-by-count":3,"title":["Structural tests of slave clock gating in low-power flip-flop"],"prefix":"10.1109","author":[{"given":"Baosheng","family":"Wang","sequence":"first","affiliation":[]},{"given":"Jayalakshmi","family":"Rajaraman","sequence":"additional","affiliation":[]},{"given":"Kanwaldeep","family":"Sobti","sequence":"additional","affiliation":[]},{"given":"Derrick","family":"Losli","sequence":"additional","affiliation":[]},{"given":"Jeff","family":"Rearick","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"415","DOI":"10.1109\/81.841927","article-title":"Clock-gating and its application to low power design of sequential circuits","volume":"47","author":"wu","year":"2000","journal-title":"IEEE Transactions on Circuits and System I Fundamental Theory and Applications"},{"key":"ref3","article-title":"Power Optimizations for a 45nm Processor Core","author":"naffziger","year":"2007","journal-title":"invited talk at University of Berkley"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699203"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"294","DOI":"10.1049\/el:20000268","article-title":"low power flip-flop with clock gating on master and slave latches","volume":"36","author":"strollo","year":"2000","journal-title":"Electronics Letters"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1982.1051686"},{"journal-title":"Low Power Flip Flop Through Partially Gated Slave Clock","year":"2010","author":"naffziger","key":"ref5"},{"journal-title":"Essentials of Electronic Testing For Digital Memory & Mixed-Signal VLSI Circuits","year":"2000","author":"bushnell","key":"ref8"},{"key":"ref7","first-page":"164","article-title":"Complex clock gating with integrated clock gating logic cell","author":"bhurada","year":"2007","journal-title":"International Conference on Design & Technology of Integrated System in Nanoscale Era (DTIS)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IWV.1999.760472"},{"key":"ref9","first-page":"130","article-title":"Test and debug features of the AMD-K7TM microprocessor","author":"wood","year":"1999","journal-title":"Proceedings of IEEE International Test Conference"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1010394"}],"event":{"name":"2011 IEEE VLSI Test Symposium (VTS)","start":{"date-parts":[[2011,5,1]]},"location":"Dana Point, CA, USA","end":{"date-parts":[[2011,5,5]]}},"container-title":["29th VLSI Test Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5772241\/5783722\/05783730.pdf?arnumber=5783730","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T01:16:12Z","timestamp":1497921372000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5783730\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/vts.2011.5783730","relation":{},"subject":[],"published":{"date-parts":[[2011,5]]}}}