{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T23:12:29Z","timestamp":1725750749830},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,4]]},"DOI":"10.1109\/vts.2008.13","type":"proceedings-article","created":{"date-parts":[[2008,5,5]],"date-time":"2008-05-05T20:30:16Z","timestamp":1210019416000},"page":"79-84","source":"Crossref","is-referenced-by-count":38,"title":["On the Detectability of Scan Chain Internal Faults An Industrial Case Study"],"prefix":"10.1109","author":[{"given":"Fan","family":"Yang","sequence":"first","affiliation":[]},{"given":"Sreejit","family":"Chakravarty","sequence":"additional","affiliation":[]},{"given":"Narendra","family":"Devta-Prasanna","sequence":"additional","affiliation":[]},{"given":"Sudhakar M","family":"Reddy","sequence":"additional","affiliation":[]},{"given":"Irith","family":"Pomeranz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1986.295040"},{"key":"2","first-page":"462","article-title":"a logic design structure for lsi testability","author":"eichelberger","year":"1977","journal-title":"Proc 24th Des Autom Conf"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/IDDQ.1997.633004"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223600"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1995.512637"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529889"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/92.250192"},{"year":"0","key":"4"},{"key":"9","first-page":"364","article-title":"atpg for scan chain latches and flip-flops","author":"makar","year":"1997","journal-title":"Proc VTS"},{"key":"8","article-title":"checking experiments for scan chain latches and flip-flops","author":"makar","year":"1996","journal-title":"CRC Technical Report"},{"key":"11","first-page":"194","article-title":"design and implementation of a full testable cmos d-latches","author":"aissi","year":"1995","journal-title":"IEEE 5th IPFA"}],"event":{"name":"26th IEEE VLSI Test Symposium (vts 2008)","start":{"date-parts":[[2008,4,27]]},"location":"San Diego, CA, USA","end":{"date-parts":[[2008,5,1]]}},"container-title":["26th IEEE VLSI Test Symposium (vts 2008)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4511672\/4511673\/04511700.pdf?arnumber=4511700","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T22:07:19Z","timestamp":1489702039000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4511700\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/vts.2008.13","relation":{},"ISSN":["1093-0167"],"issn-type":[{"type":"print","value":"1093-0167"}],"subject":[],"published":{"date-parts":[[2008,4]]}}}