{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T05:29:19Z","timestamp":1725514159967},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/vts.2006.51","type":"proceedings-article","created":{"date-parts":[[2006,5,25]],"date-time":"2006-05-25T16:26:01Z","timestamp":1148574361000},"page":"166-171","source":"Crossref","is-referenced-by-count":14,"title":["On the Automation of the Test Flow of Complex SoCs"],"prefix":"10.1109","author":[{"given":"D.","family":"Appello","sequence":"first","affiliation":[]},{"given":"V.","family":"Tancorre","sequence":"additional","affiliation":[]},{"given":"P.","family":"Bernardi","sequence":"additional","affiliation":[]},{"given":"M.","family":"Grosso","sequence":"additional","affiliation":[]},{"given":"M.","family":"Rebaudengo","sequence":"additional","affiliation":[]},{"given":"M.S.","family":"Reorda","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.305"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990266"},{"year":"0","key":"13"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998361"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2004.25"},{"key":"12","first-page":"1213","article-title":"An SOC test integration platform and its industrial realization","author":"cheng","year":"2004","journal-title":"IEEE International Test Conference"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270861"},{"journal-title":"IEEE P1500 Standard for Embedded Core Test (SECT)","year":"0","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/35.769283"},{"key":"10","doi-asserted-by":"crossref","first-page":"140","DOI":"10.1109\/IEMT.2004.1321646","article-title":"New design-to-test software strategies accelerate time-to-market","author":"lam","year":"2004","journal-title":"IEEE\/CPMT\/SEMI International Electronic Manufacturing Test Symposium"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1214350"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2004.24"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1252857"},{"journal-title":"IEEE 1450 - Standard Test Interface Language (STIL)","year":"0","key":"4"},{"key":"9","article-title":"A multi-layer test program to improve EDA-ATE link","author":"bertuzzi","year":"2005","journal-title":"European Manufacturing Test Conference (EMTC)"},{"key":"8","article-title":"Hierarchical I-IP network for STAR memory system diagnosis","author":"yessayan","year":"2004","journal-title":"2nd IEEE International Workshop of Infrastructure IP"}],"event":{"name":"24th IEEE VLSI Test Symposium","location":"Berkeley, CA, USA"},"container-title":["24th IEEE VLSI Test Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10758\/33903\/01617584.pdf?arnumber=1617584","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T02:01:34Z","timestamp":1497664894000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1617584\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/vts.2006.51","relation":{},"subject":[]}}