{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T10:35:02Z","timestamp":1725705302476},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/vlsic.2015.7231254","type":"proceedings-article","created":{"date-parts":[[2015,9,3]],"date-time":"2015-09-03T17:50:20Z","timestamp":1441302620000},"page":"C182-C183","source":"Crossref","is-referenced-by-count":4,"title":["A 6.4Gb\/s\/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface"],"prefix":"10.1109","author":[{"given":"Chang-Kyo","family":"Lee","sequence":"first","affiliation":[]},{"given":"Minsu","family":"Ahn","sequence":"additional","affiliation":[]},{"given":"Daesik","family":"Moon","sequence":"additional","affiliation":[]},{"given":"Kiho","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Yoon-Joo","family":"Eom","sequence":"additional","affiliation":[]},{"given":"Won-Young","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Jongmin","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Sanghyuk","family":"Yoon","sequence":"additional","affiliation":[]},{"given":"Baekkyu","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Seokhong","family":"Kwon","sequence":"additional","affiliation":[]},{"given":"Joon-Young","family":"Park","sequence":"additional","affiliation":[]},{"given":"Seung-Jun","family":"Bae","sequence":"additional","affiliation":[]},{"given":"Yong-Cheol","family":"Bae","sequence":"additional","affiliation":[]},{"given":"Jung-Hwan","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Seong-Jin","family":"Jang","sequence":"additional","affiliation":[]},{"given":"Gyoyoung","family":"Jin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810029"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892189"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2249812"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2000.852869"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757500"},{"key":"ref2","first-page":"238","article-title":"A 1.0625 Gb\/s transceiver with 2-oversampling and transmit signal pre-emphasis","author":"fiedler","year":"1997","journal-title":"IEEE ISSCC"},{"key":"ref1","first-page":"44","article-title":"A 1.2V 1.6Gb\/s\/pin 4Gb Low Power DDR3 SDRAM with Input Skew Calibration and Enhanced Refresh Control Scheme","author":"bae","year":"2012","journal-title":"IEEE ISSCC"}],"event":{"name":"2015 Symposium on VLSI Circuits","start":{"date-parts":[[2015,6,17]]},"location":"Kyoto, Japan","end":{"date-parts":[[2015,6,19]]}},"container-title":["2015 Symposium on VLSI Circuits (VLSI Circuits)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7196579\/7231231\/07231254.pdf?arnumber=7231254","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T01:25:47Z","timestamp":1490405147000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7231254\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/vlsic.2015.7231254","relation":{},"subject":[],"published":{"date-parts":[[2015,6]]}}}