{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,12]],"date-time":"2024-12-12T05:53:40Z","timestamp":1733982820348,"version":"3.30.2"},"reference-count":54,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2024,12,1]],"date-time":"2024-12-01T00:00:00Z","timestamp":1733011200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,12,1]],"date-time":"2024-12-01T00:00:00Z","timestamp":1733011200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,12,1]],"date-time":"2024-12-01T00:00:00Z","timestamp":1733011200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"The ASEAN IVO project, \u201cArtificial Intelligence Powered Comprehensive Cyber-Security for Smart Healthcare Systems (AIPOSH),\u201d"},{"DOI":"10.13039\/501100012389","name":"National Institute of Information and Communications Technology","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100012389","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2024,12]]},"DOI":"10.1109\/tvlsi.2024.3444851","type":"journal-article","created":{"date-parts":[[2024,8,27]],"date-time":"2024-08-27T17:29:55Z","timestamp":1724779795000},"page":"2341-2354","source":"Crossref","is-referenced-by-count":0,"title":["Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC"],"prefix":"10.1109","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8011-5518","authenticated-orcid":false,"given":"Thai-Ha","family":"Tran","sequence":"first","affiliation":[{"name":"Department of Computer and Network Engineering, The University of Electro-Communications, Tokyo, Japan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8761-6398","authenticated-orcid":false,"given":"Ba-Anh","family":"Dao","sequence":"additional","affiliation":[{"name":"Institute of Scientific and Technological Research and Application, Academy of Cryptography Techniques, Hanoi, Vietnam"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3227-9117","authenticated-orcid":false,"given":"Duc-Hung","family":"Le","sequence":"additional","affiliation":[{"name":"Faculty of Electronics and Telecommunications, The University of Science, Vietnam National University Ho Chi Minh City, Ho Chi Minh City, Vietnam"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0944-8701","authenticated-orcid":false,"given":"Van-Phuc","family":"Hoang","sequence":"additional","affiliation":[{"name":"Institute of System Integration, Le Quy Don Technical University, Hanoi, Vietnam"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4078-0836","authenticated-orcid":false,"given":"Trong-Thuc","family":"Hoang","sequence":"additional","affiliation":[{"name":"Department of Computer and Network Engineering, The University of Electro-Communications, Tokyo, Japan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5255-4919","authenticated-orcid":false,"given":"Cong-Kha","family":"Pham","sequence":"additional","affiliation":[{"name":"Department of Computer and Network Engineering, The University of Electro-Communications, Tokyo, Japan"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/TVLSI.2022.3203307"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/TVLSI.2023.3288754"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TCAD.2021.3065915"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/ACCESS.2023.3246491"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/JIOT.2023.3265683"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/TVLSI.2023.3340553"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/JETCAS.2021.3077887"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1007\/978-0-387-38162-6"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1145\/3304080.3304082"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ACCESS.2021.3079960"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1007\/978-3-030-75343-6"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/ISCAS.2009.5118398"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/TETC.2020.3045802"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/ICCAD45719.2019.8942112"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/ACCESS.2021.3126703"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1007\/978-3-030-10970-7_9"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/TVLSI.2023.3339810"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/ACCESS.2023.3301178"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/ACCESS.2023.3311370"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/TVLSI.2022.3175180"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/ISCAS46773.2023.10181621"},{"volume-title":"Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.19)","year":"2021","key":"ref22"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1007\/978-3-662-48324-4_25"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.46586\/tches.v2018.i1.209-237"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/TCAD.2021.3112884"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.46586\/tches.v2019.i1.259-282"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1145\/3569562.3569564"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.46586\/tches.v2021.i3.552-598"},{"volume-title":"Chipyard: An Agile RISC-V SoC Design Framework With In-Order Cores, Out-of-Order Cores, Accelerators, and More","year":"2020","key":"ref29"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1145\/3457388.3458657"},{"volume-title":"Security of Block Cipher: From Algorithm Design to Hardware Implementation","year":"2016","author":"Sakiyama","key":"ref31"},{"key":"ref32","first-page":"1","article-title":"RFTC: Runtime frequency tuning countermeasure using FPGA dynamic reconfiguration to mitigate power analysis attacks","volume-title":"Proc. 56th ACM\/IEEE Design Autom. Conf. (DAC)","author":"Jayasinghe"},{"doi-asserted-by":"publisher","key":"ref33","DOI":"10.1109\/TCAD.2023.3237957"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1109\/TCAD.2004.831584"},{"volume-title":"MMCM and PLL Dynamic Reconfiguration XAPP888 (v1.8)","year":"2019","author":"Tatsukawa","key":"ref35"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1007\/978-3-319-55589-8_16"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1007\/978-3-030-77222-2_6"},{"volume-title":"7 Series FPGAs Clocking Resources User Guide UG472 (v1.14)","year":"2018","key":"ref38"},{"volume-title":"X-Series Signal Analyzer Spectrum Analyzer Mode User\u2019s and Programmer\u2019s Reference","year":"2018","key":"ref39"},{"doi-asserted-by":"publisher","key":"ref40","DOI":"10.6028\/nist.sp.800-22"},{"volume-title":"Proc. Bundesamt Fur Sicherheit der Informationstechnik (BSI)","author":"Killmann","article-title":"A proposal for: Functionality classes for random number generators, version 2.0","key":"ref41"},{"doi-asserted-by":"publisher","key":"ref42","DOI":"10.1109\/FPL50879.2020.00041"},{"doi-asserted-by":"publisher","key":"ref43","DOI":"10.13154\/tches.v2019.i2.107-131"},{"doi-asserted-by":"publisher","key":"ref44","DOI":"10.1007\/978-3-540-28632-5_2"},{"doi-asserted-by":"publisher","key":"ref45","DOI":"10.1007\/978-3-642-19074-2_8"},{"doi-asserted-by":"publisher","key":"ref46","DOI":"10.1109\/APCCAS.2016.7803910"},{"doi-asserted-by":"publisher","key":"ref47","DOI":"10.46586\/tches.v2022.i4.589-613"},{"doi-asserted-by":"publisher","key":"ref48","DOI":"10.1109\/mdat.2023.3298805"},{"doi-asserted-by":"publisher","key":"ref49","DOI":"10.1145\/3530054"},{"doi-asserted-by":"publisher","key":"ref50","DOI":"10.1109\/TIFS.2023.3327658"},{"doi-asserted-by":"publisher","key":"ref51","DOI":"10.1109\/TC.2022.3211437"},{"doi-asserted-by":"publisher","key":"ref52","DOI":"10.1109\/MWSCAS.2018.8624009"},{"doi-asserted-by":"publisher","key":"ref53","DOI":"10.1109\/TETC.2020.3027789"},{"doi-asserted-by":"publisher","key":"ref54","DOI":"10.46586\/tches.v2021.i4.447-473"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/10791073\/10649588.pdf?arnumber=10649588","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,11]],"date-time":"2024-12-11T21:59:49Z","timestamp":1733954389000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10649588\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12]]},"references-count":54,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3444851","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2024,12]]}}}