{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,20]],"date-time":"2024-09-20T16:01:43Z","timestamp":1726848103154},"reference-count":9,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2013,3,1]],"date-time":"2013-03-01T00:00:00Z","timestamp":1362096000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,3]]},"DOI":"10.1109\/tvlsi.2012.2190117","type":"journal-article","created":{"date-parts":[[2012,3,23]],"date-time":"2012-03-23T12:33:14Z","timestamp":1332505994000},"page":"584-588","source":"Crossref","is-referenced-by-count":89,"title":["10-bit 30-MS\/s SAR ADC Using a Switchback Switching Method"],"prefix":"10.1109","volume":"21","author":[{"given":"Guan-Ying","family":"Huang","sequence":"first","affiliation":[]},{"given":"Soon-Jyh","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Chun-Cheng","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Ying-Zu","family":"Lin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2009.5357202"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref6","first-page":"238","article-title":"An 820 $\\mu{\\rm W}$<\/tex><\/formula> 9b 40 MS\/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS","author":"giannini","year":"2008","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref5","first-page":"574","article-title":"A 6-bit 600-MS\/s 5.3-mW asynchronous ADC in 0.13-$\\mu{\\rm m}$<\/tex><\/formula> CMOS","author":"chen","year":"2006","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref8","first-page":"384","article-title":"A 10b 50 MS\/s 820 mW SAR ADC with on-chip digital calibration","author":"yoshioka","year":"2010","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"502","DOI":"10.1109\/TCSII.2010.2048387","article-title":"A 9-bit 80 MS\/s successive approximation register analog-to-digital converter with a capacitor reduction technique","volume":"57","author":"furta","year":"2010","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.760369"},{"key":"ref1","first-page":"149","article-title":"A 10-bit 500-KS\/s low power SAR ADC with splitting capacitor for bio-medical applications","author":"pang","year":"2009","journal-title":"ASSCC Proc Tech Papers"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6466554\/06172687.pdf?arnumber=6172687","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:56:14Z","timestamp":1638219374000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6172687\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":9,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2190117","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,3]]}}}