{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,5]],"date-time":"2025-04-05T10:45:17Z","timestamp":1743849917657,"version":"3.37.3"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100010663","name":"European Union\u2019s Horizon 2020 ERC project NeuroAgents","doi-asserted-by":"publisher","award":["724295"],"id":[{"id":"10.13039\/100010663","id-type":"DOI","asserted-by":"publisher"}]},{"name":"European Union\u2019s Horizon 2020 Research and Innovation Programme","award":["871737"]},{"name":"Toshiba Corporation"},{"name":"H2020 MeM-Scales Project","award":["871371"]},{"DOI":"10.13039\/501100011688","name":"ECSEL Joint Undertaking","doi-asserted-by":"crossref","award":["826655"],"id":[{"id":"10.13039\/501100011688","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2021,1]]},"DOI":"10.1109\/tcsi.2020.3035575","type":"journal-article","created":{"date-parts":[[2020,11,13]],"date-time":"2020-11-13T21:21:07Z","timestamp":1605302467000},"page":"45-56","source":"Crossref","is-referenced-by-count":62,"title":["Ultra-Low-Power FDSOI Neural Circuits for Extreme-Edge Neuromorphic Intelligence"],"prefix":"10.1109","volume":"68","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5036-1969","authenticated-orcid":false,"given":"Arianna","family":"Rubino","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7123-5761","authenticated-orcid":false,"given":"Can","family":"Livanelioglu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0264-5622","authenticated-orcid":false,"given":"Ning","family":"Qiao","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5400-067X","authenticated-orcid":false,"given":"Melika","family":"Payvand","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7109-1689","authenticated-orcid":false,"given":"Giacomo","family":"Indiveri","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2019.8852279"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1063\/1.5142089"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2017.2754383"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5536980"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.5607\/en.2017.26.4.179"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2004.832719"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1039\/C8FD00114F"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/BioCAS.2016.7833854"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1049\/el:20083145"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702500"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2313954"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2019.2925454"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2019.2928376"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2017.2759700"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2019.2953001"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS46596.2019.8964713"},{"journal-title":"Analog VLSI and Neural Systems","year":"1989","author":"mead","key":"ref15"},{"key":"ref16","article-title":"Analog VLSI implementation of neural networks","author":"vittoz","year":"1996","journal-title":"Handbook of Neural Computation"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.7551\/mitpress\/1250.001.0001"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2017.7966124"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2014.2379294"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1152\/jn.00686.2005"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.jcss.2004.04.001"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2011.00073"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2444094"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.isci.2018.06.010"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/s00422-008-0264-7"},{"key":"ref5","article-title":"Fast and efficient asynchronous neural computation with adapting spiking neural networks","author":"zambrano","year":"2016","journal-title":"arXiv 1609 02053"},{"key":"ref8","first-page":"787","article-title":"Long short-term memory and learning-to-learn in networks of spiking neurons","author":"bellec","year":"2018","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.cosrev.2009.03.005"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/359576.359579"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/5.58356"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.371968"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/BIOCAS.2009.5372072"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2008.4616748"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5118221"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1162\/neco.2007.19.10.2581"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS46596.2019.8965192"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/BIOCAS.2006.4600325"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5118408"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1206342"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/9316996\/09259075.pdf?arnumber=9259075","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:03:37Z","timestamp":1642003417000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9259075\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1]]},"references-count":41,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2020.3035575","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2021,1]]}}}