{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T12:05:27Z","timestamp":1740139527844,"version":"3.37.3"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61604180"],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Macao Science & Technology Development Fund","award":["117\/2016\/A3"]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1109\/tcsi.2018.2859027","type":"journal-article","created":{"date-parts":[[2018,8,30]],"date-time":"2018-08-30T19:08:03Z","timestamp":1535656083000},"page":"3606-3616","source":"Crossref","is-referenced-by-count":14,"title":["A 0.19 mm2<\/sup> 10 b 2.3 GS\/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS"],"prefix":"10.1109","volume":"65","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8298-3244","authenticated-orcid":false,"given":"Yan","family":"Zhu","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7635-1101","authenticated-orcid":false,"given":"Chi-Hang","family":"Chan","sequence":"additional","affiliation":[]},{"given":"Zi-Hao","family":"Zheng","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7232-1255","authenticated-orcid":false,"given":"Cheng","family":"Li","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5761-2209","authenticated-orcid":false,"given":"Jian-Yu","family":"Zhong","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2821-648X","authenticated-orcid":false,"given":"Rui P.","family":"Martins","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917427"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942059"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757479"},{"key":"ref13","first-page":"378","article-title":"A 90 GS\/s 8 b 667 mW \n$64\\times $\n interleaved SAR ADC in 32 nm digital SOI CMOS","author":"kull","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2519397"},{"journal-title":"CMOS Data Converters for Communications","year":"2000","author":"gustavsson","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2002548"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.880372"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2211695"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2464684"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2239005"},{"key":"ref6","first-page":"464","article-title":"An 11 b 3.6 GS\/s time-interleaved SAR ADC in 65 nm CMOS","author":"janssen","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164961"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"584","DOI":"10.1109\/TVLSI.2012.2190117","article-title":"10-bit 30-MS\/s SAR ADC using a switchback switching method","volume":"21","author":"huang","year":"2012","journal-title":"IEEE Trans Very Large Scale Integration (VLSI) Syst"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2362851"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757481"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2466475"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2747758"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2522762"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2452331"},{"key":"ref24","first-page":"314","article-title":"A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time","author":"schinkel","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708780"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/8485519\/08452156.pdf?arnumber=8452156","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:10:03Z","timestamp":1642003803000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8452156\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11]]},"references-count":24,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2018.2859027","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2018,11]]}}}