{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T10:25:18Z","timestamp":1742639118794,"version":"3.37.3"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2017,7,1]],"date-time":"2017-07-01T00:00:00Z","timestamp":1498867200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003711","name":"Ministry of Science and Technology in Taiwan","doi-asserted-by":"publisher","award":["104-2218-E-009-007"],"id":[{"id":"10.13039\/501100003711","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Ministry of Education in Taiwan under the ATU Program"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/tcsi.2017.2681738","type":"journal-article","created":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T02:08:46Z","timestamp":1490321326000},"page":"1791-1802","source":"Crossref","is-referenced-by-count":18,"title":["A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist"],"prefix":"10.1109","volume":"64","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3348-0787","authenticated-orcid":false,"given":"Shang-Lin","family":"Wu","sequence":"first","affiliation":[]},{"given":"Kuang-Yu","family":"Li","sequence":"additional","affiliation":[]},{"given":"Po-Tsang","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Wei","family":"Hwang","sequence":"additional","affiliation":[]},{"given":"Ming-Hsien","family":"Tu","sequence":"additional","affiliation":[]},{"given":"Sheng-Chi","family":"Lung","sequence":"additional","affiliation":[]},{"given":"Wei-Sheng","family":"Peng","sequence":"additional","affiliation":[]},{"given":"Huan-Shun","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Kuen-Di","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Yung-Shin","family":"Kao","sequence":"additional","affiliation":[]},{"given":"Ching-Te","family":"Chuang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2316219"},{"key":"ref10","first-page":"112","article-title":"A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques","author":"chen","year":"2012","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref11","first-page":"158","article-title":"A 45nm 0.6V cross-point 8T SRAM with negative biased read\/write assist","author":"yabuuchi","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746307"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2332267"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2014.6948972"},{"key":"ref15","first-page":"201","article-title":"A 40nm, 454MHz 114 fJ\/bit area-efficient SRAM memory with integrated charge pump","author":"rooseleer","year":"2013","journal-title":"Proc ESSCIRC"},{"key":"ref16","first-page":"622","article-title":"A 5.6GHz 64kB dual-read data cache for the POWER6TM processor","author":"davis","year":"2006","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373424"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5434076"},{"key":"ref19","first-page":"251","article-title":"A Pico-joule class, 1 GHz, 32 kByte \n$\\times64$\nb DSP SRAM with self-reverse bias","author":"bhavnagarwala","year":"2003","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2318518"},{"journal-title":"Sub-Threshold Design for Ultra Low-Power Systems","year":"2006","author":"wang","key":"ref4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2336531"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2012.6398351"},{"key":"ref6","first-page":"230","article-title":"A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry","author":"kar","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746310"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4586011"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2231017"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2187474"},{"key":"ref2","first-page":"197","article-title":"A high-performance low VM1N 55nm 512kb disturb-free 8T SRAM with adaptive VVSS control","author":"yang","year":"2011","journal-title":"Proc IEEE Int Syst Chip Conf (SoCC)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2091321"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469239"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342773"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487753"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020201"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131655"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705289"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055398"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2349977"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8919\/7956380\/07885536.pdf?arnumber=7885536","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:38:43Z","timestamp":1641987523000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7885536\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":30,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2017.2681738","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"type":"print","value":"1549-8328"},{"type":"electronic","value":"1558-0806"}],"subject":[],"published":{"date-parts":[[2017,7]]}}}