{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T06:10:03Z","timestamp":1742278203143,"version":"3.40.1"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/tc.2012.255","type":"journal-article","created":{"date-parts":[[2014,3,26]],"date-time":"2014-03-26T18:04:30Z","timestamp":1395857070000},"page":"718-733","source":"Crossref","is-referenced-by-count":53,"title":["Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing"],"prefix":"10.1109","volume":"63","member":"263","reference":[{"key":"ref1","first-page":"684","article-title":"Route Packets, Not Wires: On-Chip Interconnection Networks","volume-title":"Proc. 38th Design Automation Conf.","author":"Dally"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1007\/b105353"},{"volume-title":"Interconnection Networks: An Engineering Approach","year":"2003","author":"Duato","key":"ref3"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/5.929647"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/TC.2008.142"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/3DIC.2012.6263037"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/ICPP.2007.79"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/DATE.2009.5090625"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/TVLSI.2007.893649"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ISCA.2008.12"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/HPCA.2009.4798273"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/ISCA.1995.524546"},{"key":"ref13","first-page":"72","article-title":"The Parsec Benchmark Suite: Characterization and Architectural Implications","volume-title":"Proc. 17th Int\u2019l Conf. Parallel Architectures and Compilation Techniques","author":"Bienia"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/IISWC.2008.4636090"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1145\/1393921.1393988"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/ISCA.2003.1206999"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1145\/1105734.1105747"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/71.246072"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/ISVLSI.2008.18"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1016\/j.sysarc.2010.08.002"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/71.689441"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/71.744844"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1007\/BFb0032940"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1109\/NOCS.2012.10"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/AHS.2011.5963937"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1145\/1999946.1999958"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1109\/NOCS.2009.5071446"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1109\/HICSS.1994.323174"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1109\/71.250114"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.3923\/jas.2007.3410.3419"},{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1109\/2.191995"},{"doi-asserted-by":"publisher","key":"ref32","DOI":"10.1109\/L-CA.2008.6"},{"doi-asserted-by":"publisher","key":"ref33","DOI":"10.1109\/71.298203"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1109\/PDP.2010.77"},{"doi-asserted-by":"publisher","key":"ref35","DOI":"10.1109\/MICRO.2002.1176258"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1109\/ISCA.2006.18"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1109\/nocs.2009.5071459"},{"doi-asserted-by":"publisher","key":"ref38","DOI":"10.1109\/ISCA.2008.13"},{"doi-asserted-by":"publisher","key":"ref39","DOI":"10.1109\/71.877831"},{"doi-asserted-by":"publisher","key":"ref40","DOI":"10.1109\/MICRO.2007.33"},{"doi-asserted-by":"publisher","key":"ref41","DOI":"10.1109\/DATE.2010.5457230"},{"doi-asserted-by":"publisher","key":"ref42","DOI":"10.1109\/MM.2005.35"},{"doi-asserted-by":"publisher","key":"ref43","DOI":"10.1109\/MICRO.2004.21"},{"doi-asserted-by":"publisher","key":"ref44","DOI":"10.1016\/j.mejo.2009.10.006"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/6778691\/06338924.pdf?arnumber=6338924","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T05:41:50Z","timestamp":1742276510000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6338924\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":44,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tc.2012.255","relation":{},"ISSN":["0018-9340"],"issn-type":[{"type":"print","value":"0018-9340"}],"subject":[],"published":{"date-parts":[[2014,3]]}}}