{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T11:44:12Z","timestamp":1725795852928},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/socc.2011.6085080","type":"proceedings-article","created":{"date-parts":[[2011,11,23]],"date-time":"2011-11-23T16:54:27Z","timestamp":1322067267000},"page":"197-200","source":"Crossref","is-referenced-by-count":4,"title":["A high-performance low V<inf>MIN<\/inf> 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control"],"prefix":"10.1109","author":[{"given":"Hao-I","family":"Yang","sequence":"first","affiliation":[]},{"given":"Shih-Chi","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Mao-Chih","family":"Hsia","sequence":"additional","affiliation":[]},{"given":"Yung-Wei","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Yi-Wei","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Chien-Hen","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Chi-Shin","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Geng-Cing","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Yin-Nien","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Ching-Te","family":"Chuang","sequence":"additional","affiliation":[]},{"given":"Wei","family":"Hwang","sequence":"additional","affiliation":[]},{"given":"Shyh-Jye","family":"Jou","sequence":"additional","affiliation":[]},{"given":"Nan-Chun","family":"Lien","sequence":"additional","affiliation":[]},{"given":"Hung-Yu","family":"Li","sequence":"additional","affiliation":[]},{"given":"Kuen-Di","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Wei-Chiang","family":"Shih","sequence":"additional","affiliation":[]},{"given":"Ya-Ping","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Wen-Ta","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Chih-Chiang","family":"Hsu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523220"},{"key":"2","first-page":"158","article-title":"A 45nm 0.6V cross-point 8T SRAM with negative biased read\/write assist","author":"yabuuchi","year":"2009","journal-title":"IEEE Symp VLSI Circuits"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469239"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2029114"},{"journal-title":"IEEE Trans Circuits Syst I Reg Papers","article-title":"An 8T differential SRAM with improved noise margin for bit-interleaving in 65nm CMOS","year":"0","author":"anh-tuan","key":"5"},{"journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst","article-title":"A novel column-decoupled 8T cell for low-power differential and domino-based SRAM design","year":"0","author":"ramadurai","key":"4"}],"event":{"name":"2011 IEEE 24th International SOC Conference (SOCC)","start":{"date-parts":[[2011,9,26]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2011,9,28]]}},"container-title":["2011 IEEE International SOC Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6076821\/6085068\/06085080.pdf?arnumber=6085080","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T10:03:50Z","timestamp":1490090630000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6085080\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/socc.2011.6085080","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}