{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,14]],"date-time":"2024-08-14T11:52:15Z","timestamp":1723636335239},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,12]]},"DOI":"10.1109\/reconfig.2017.8279792","type":"proceedings-article","created":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T22:32:24Z","timestamp":1517869944000},"source":"Crossref","is-referenced-by-count":21,"title":["Fast generation of high throughput customized deep learning accelerators on FPGAs"],"prefix":"10.1109","author":[{"given":"Hanqing","family":"Zeng","sequence":"first","affiliation":[]},{"given":"Chi","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Viktor","family":"Prasanna","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Fast algorithms for convolutional neural networks","author":"lavin","year":"2015","journal-title":"CoRR vol abs\/1509 09308"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021727"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645545"},{"key":"ref13","author":"zeng","year":"2017","journal-title":"Optimizing Frequency Domain Implementation of CNNs on FPGAs"},{"key":"ref14","year":"2015","journal-title":"Intel Inc Xeon+FPGA Platform for the Data Center"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2010.2044260"},{"key":"ref16","article-title":"Very efficient training of convolutional neural networks using fast fourier transform and overlap-and-add","author":"highlander","year":"2016","journal-title":"CoRR vol abs\/1601 06815"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"240","DOI":"10.1145\/2684746.2689068","article-title":"Energy and memory efficient mapping of bitonic sorting on fpga","author":"chen","year":"2015","journal-title":"Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays ser FPGA '15"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1953.tb01433.x"},{"key":"ref19","article-title":"Scalable and modularized rtl compilation of convolutional neural networks onto fpga","author":"ma","year":"2016","journal-title":"International Conference on Field Programmable Logic and Applications (FPL)"},{"key":"ref4","article-title":"Tensorflow: Large-scale machine learning on heterogeneous distributed systems","author":"abadi","year":"2016","journal-title":"CoRR vol abs\/1603 04467"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2647868.2654889"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2014.7041004"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1145\/2684746.2689060","article-title":"Optimizing fpga-based accelerator design for deep convolutional neural networks","author":"zhang","year":"2015","journal-title":"Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1145\/2847263.2847276","article-title":"Throughput-optimized opencl-based fpga accelerator for large-scale convolutional neural networks","author":"suda","year":"2016","journal-title":"Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"ref2","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2014","journal-title":"CoRR vol abs\/1409 1556"},{"key":"ref1","first-page":"1097","article-title":"Imagenet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Advances in neural information processing systems"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783720"}],"event":{"name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","location":"Cancun","start":{"date-parts":[[2017,12,4]]},"end":{"date-parts":[[2017,12,6]]}},"container-title":["2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8268902\/8279767\/08279792.pdf?arnumber=8279792","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,25]],"date-time":"2022-01-25T21:25:57Z","timestamp":1643145957000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8279792\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2017.8279792","relation":{},"subject":[],"published":{"date-parts":[[2017,12]]}}}