{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T07:12:35Z","timestamp":1725433955375},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,12]]},"DOI":"10.1109\/reconfig.2017.8279772","type":"proceedings-article","created":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T22:32:24Z","timestamp":1517869944000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Adaptive software-augmented hardware reconfiguration with dataflow design automation"],"prefix":"10.1109","author":[{"given":"Claudio","family":"Rubattu","sequence":"first","affiliation":[]},{"given":"Francesca","family":"Palumbo","sequence":"additional","affiliation":[]},{"given":"Maxime","family":"Pelcat","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Stream-Dataflow Acceleration Intl Symp on Computer Architecture","year":"2017","author":"nowatzki","key":"ref4"},{"journal-title":"Enabling dynamic and partial reconfiguration in Xilinx SDSoC Conf on ReConFigurable Computing and FPGAs","year":"2016","author":"kalb","key":"ref3"},{"journal-title":"Analysis of a Heterogeneous Multi-Core Multi-HW-Accelerator-Based System Designed Using PREESM and SDSoC To appear in Conf on Reconfigurable Communication-centric Systems-on-Chip","year":"2017","author":"suriano","key":"ref6"},{"journal-title":"Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? Intl Conf on Pervasive Intelligence and Computing","year":"2016","author":"jain","key":"ref5"},{"journal-title":"Coarse grained reconfigurable architectures in the past 25 years Overview and classification Conf on Embedded Computer Systems Architectures Modeling and Simulation","year":"2016","author":"wijtvliet","key":"ref8"},{"journal-title":"Challenging the Best HEVC Fractional Pixel FPGA Interpolators with Reconfigurable and Multi-frequency Approximate Computing IEEE Embedded Systems Letters","year":"2017","author":"sau","key":"ref7"},{"journal-title":"Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain Conf on ReConFigurable Computing and FPGAs","year":"2015","author":"sau","key":"ref2"},{"journal-title":"Cross-layer design of reconfigurable cyber-physical systems Design Automation & Test in Europe Conference & Exhibition","year":"2017","author":"masin","key":"ref1"}],"event":{"name":"2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2017,12,4]]},"location":"Cancun","end":{"date-parts":[[2017,12,6]]}},"container-title":["2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8268902\/8279767\/08279772.pdf?arnumber=8279772","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,3,5]],"date-time":"2018-03-05T22:11:31Z","timestamp":1520287891000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8279772\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2017.8279772","relation":{},"subject":[],"published":{"date-parts":[[2017,12]]}}}