{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T12:48:45Z","timestamp":1730292525258,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,12]]},"DOI":"10.1109\/reconfig.2009.58","type":"proceedings-article","created":{"date-parts":[[2010,1,20]],"date-time":"2010-01-20T16:06:20Z","timestamp":1264003580000},"page":"243-248","source":"Crossref","is-referenced-by-count":10,"title":["DPL on Stratix II FPGA: What to Expect?"],"prefix":"10.1109","author":[{"given":"Laurent","family":"Sauvage","sequence":"first","affiliation":[]},{"given":"Maxime","family":"Nassar","sequence":"additional","affiliation":[]},{"given":"Sylvain","family":"Guilley","sequence":"additional","affiliation":[]},{"given":"Florent","family":"Flament","sequence":"additional","affiliation":[]},{"given":"Jean-Luc","family":"Danger","sequence":"additional","affiliation":[]},{"given":"Yves","family":"Mathieu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-008-9017-z"},{"key":"ref11","first-page":"396","article-title":"Divided Backend Duplication Methodology for Balanced Dual Rail Routing","volume":"5154","year":"2008","journal-title":"CHES Ser LNCS"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2008.4559042"},{"journal-title":"DES","year":"1999","key":"ref13"},{"journal-title":"Altera FPGA designer","year":"0","key":"ref14"},{"journal-title":"SASEBO","year":"0","key":"ref15"},{"journal-title":"Sourceforge","year":"2009","key":"ref16"},{"key":"ref17","first-page":"388","article-title":"Differential Power Analysis","volume":"1666","author":"kocher","year":"1999","journal-title":"Proc CRYPTO '99 LNCS"},{"key":"ref18","first-page":"16","article-title":"Correlation Power Analysis with a Leakage Model","volume":"3156","author":"brier","year":"2004","journal-title":"CHES Ser LNCS"},{"key":"ref19","first-page":"13","article-title":"Template Attacks","volume":"2523","author":"chari","year":"2002","journal-title":"CHES Ser LNCS"},{"key":"ref4","first-page":"242","article-title":"Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage","volume":"4249","author":"chen","year":"2006","journal-title":"CHES Ser LNCS"},{"key":"ref3","first-page":"172","article-title":"Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints","volume":"3659","author":"popp","year":"2005","journal-title":"Proceedings of CHES'05 ser LNCS"},{"key":"ref6","first-page":"224","article-title":"Synthesis of Secure FPGA Implementations","author":"tiri","year":"0"},{"key":"ref5","first-page":"95","article-title":"Masking and Dual Rail Logic Don't Add Up","volume":"4727","author":"schaumont","year":"2007","journal-title":"CHES Ser LNCS"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289831"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SSIRI.2008.31"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855939"},{"key":"ref1","first-page":"309","article-title":"Improved Higher-Order Side-Channel Attacks With FPGA Experiments","volume":"3659","author":"peeters","year":"2005","journal-title":"CHES Ser LNCS"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1502781.1502784"},{"key":"ref20","article-title":"Mutual Information Analysis - A Universal Differential Side-Channel Attack","author":"gierlichs","year":"2007","journal-title":"Cryptology ePrint Archive Report"},{"key":"ref21","first-page":"499","article-title":"Theoretical and Practical Aspects of Mutual Information Based Side Channel Analysis","volume":"5536","author":"prouff","year":"2009","journal-title":"ACNS Ser LNCS"}],"event":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2009,12,9]]},"location":"Cancun, Mexico","end":{"date-parts":[[2009,12,11]]}},"container-title":["2009 International Conference on Reconfigurable Computing and FPGAs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5379688\/5381991\/05382059.pdf?arnumber=5382059","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T21:44:45Z","timestamp":1489873485000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5382059\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2009.58","relation":{},"subject":[],"published":{"date-parts":[[2009,12]]}}}