{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T12:48:23Z","timestamp":1730292503229,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,12]]},"DOI":"10.1109\/reconfig.2008.28","type":"proceedings-article","created":{"date-parts":[[2009,1,14]],"date-time":"2009-01-14T13:57:00Z","timestamp":1231941420000},"page":"115-120","source":"Crossref","is-referenced-by-count":5,"title":["The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture"],"prefix":"10.1109","author":[{"given":"Umer","family":"Farooq","sequence":"first","affiliation":[]},{"given":"Zied","family":"Marrakchi","sequence":"additional","affiliation":[]},{"given":"Hayder","family":"Mrabet","sequence":"additional","affiliation":[]},{"given":"Habib","family":"Mehrez","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","article-title":"introduction to algorithms","author":"cormen","year":"1990","journal-title":"MIT Press Cambridge"},{"year":"0","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"14","first-page":"1217","author":"rose","year":"1990","journal-title":"Architecture of field programmable gate arrays The effect of logic functionality on area efficiency"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"12","first-page":"321","article-title":"efficient tree topology for fpga interconnect network","author":"marrakchi","year":"2008","journal-title":"ACM Great Lakes Symposium on VLSI"},{"key":"3","article-title":"the effect of lut and cluster size on deep-submicron fpga performance and density","author":"ahmed","year":"2003","journal-title":"IEEE"},{"key":"2","article-title":"alliance: a complete set of cad tools for teaching vlsi design","author":"greiner","year":"1992","journal-title":"EuroChip Workshop"},{"year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"7","article-title":"performances improvement of fpga using novel multilevel hierarchical interconnection structure","author":"mrabet","year":"2006","journal-title":"ICCAD San Jose"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/43.205013"},{"key":"5","article-title":"multilevel k-way hypergraph partitioning","author":"karypis","year":"1999","journal-title":"Design Automation Conference"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"9","first-page":"9","article-title":"fpga area versus cell granularity-lookup tables and pla cells","volume":"92","author":"kouloheris","year":"1992","journal-title":"FPGA"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296405"}],"event":{"name":"2008 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2008,12,3]]},"location":"Cancun, Mexico","end":{"date-parts":[[2008,12,5]]}},"container-title":["2008 International Conference on Reconfigurable Computing and FPGAs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4731750\/4731751\/04731780.pdf?arnumber=4731780","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T11:39:02Z","timestamp":1489750742000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4731780\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,12]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2008.28","relation":{},"subject":[],"published":{"date-parts":[[2008,12]]}}}