{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T01:55:38Z","timestamp":1729648538915,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,12]]},"DOI":"10.1109\/reconfig.2008.15","type":"proceedings-article","created":{"date-parts":[[2009,1,14]],"date-time":"2009-01-14T13:57:00Z","timestamp":1231941420000},"page":"331-336","source":"Crossref","is-referenced-by-count":14,"title":["Generalised Parallel Bilinear Interpolation Architecture for Vision Systems"],"prefix":"10.1109","author":[{"given":"Suhaib A.","family":"Fahmy","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"crossref","first-page":"235","DOI":"10.1007\/s11554-007-0061-x","article-title":"realtime hardware acceleration of the trace transform","volume":"2","author":"fahmy","year":"2007","journal-title":"Journal of Real-Time Image Processing"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-32256-6_37"},{"journal-title":"Virtex-5 user guide","year":"2007","key":"10"},{"journal-title":"O-matrix webpage","year":"0","key":"1"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/HDP.2007.4283630"},{"key":"6","first-page":"408","article-title":"a real-time fpga implementation of a barrel distortion correction algorithm with bilinear interpolation","author":"gribbon","year":"2003","journal-title":"Image and Vision Computing New Zealand"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2004.10055"},{"journal-title":"Digital Image Processing","year":"2007","author":"gonzalez","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TENCON.2004.1414908"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1117\/12.526400"},{"journal-title":"IEEE International Symposium on Circuits and Systems (ISCAS)","article-title":"a hardware-efficient dual-standard vlsi architecture for me interpolation in avs and h.264","year":"2007","author":"zhou","key":"11"}],"event":{"name":"2008 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","start":{"date-parts":[[2008,12,3]]},"location":"Cancun, Mexico","end":{"date-parts":[[2008,12,5]]}},"container-title":["2008 International Conference on Reconfigurable Computing and FPGAs"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4731750\/4731751\/04731816.pdf?arnumber=4731816","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T11:42:46Z","timestamp":1497786166000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4731816\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,12]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/reconfig.2008.15","relation":{},"subject":[],"published":{"date-parts":[[2008,12]]}}}