{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T16:56:38Z","timestamp":1725382598367},"reference-count":14,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/pcee.2004.20","type":"proceedings-article","created":{"date-parts":[[2005,4,6]],"date-time":"2005-04-06T11:12:58Z","timestamp":1112785978000},"page":"45-60","source":"Crossref","is-referenced-by-count":8,"title":["Compiler Scheduling for STA-Processors"],"prefix":"10.1109","author":[{"given":"G.","family":"Cichon","sequence":"first","affiliation":[]},{"given":"P.","family":"Robelly","sequence":"additional","affiliation":[]},{"given":"H.","family":"Seidel","sequence":"additional","affiliation":[]},{"given":"M.","family":"Bronzel","sequence":"additional","affiliation":[]},{"given":"G.","family":"Fettweis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","first-page":"517","article-title":"Dynamic codewidth reduction for VLIW instruction set architectures in digital signal processors","author":"wei\ufffd","year":"1996","journal-title":"3rd Int Workshop in Signal and Image Processing (IWSIP '96)"},{"journal-title":"Supercompilers for Parallel and Vector Computers","year":"1990","author":"zima","key":"14"},{"key":"11","article-title":"GNU compiler collection internals","author":"stallman","year":"0","journal-title":"A GNU Manual"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378460"},{"key":"3","first-page":"126","article-title":"Synchronous transfer architecture (STA)","author":"cichon","year":"2004","journal-title":"Proc of Fourth International Workshop on Systems Architectures Modeling and Simulation (SAMOS'04)"},{"journal-title":"Optimizing Compilers for Modern Architectures","year":"2001","author":"allen","key":"2"},{"journal-title":"Compilers Principles Techniques and Tools","year":"1985","author":"aho","key":"1"},{"journal-title":"Beitra?ge zur Optimierten Code-erzeugung","year":"2004","author":"ro?mer","key":"10"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2570-4"},{"key":"6","first-page":"191","author":"hoogerbrugge","year":"0","journal-title":"Register File Port Requirements of Transport Triggered Architectures"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"1996","author":"hennessy","key":"5"},{"journal-title":"Microprocessor Architecture From VLIW to TTA","year":"1997","author":"corporaal","key":"4"},{"key":"9","article-title":"The IBM research parallel processor prototype (RP3): Introduction and architecture","author":"pfister","year":"1985","journal-title":"Proceedings of the 1985 International Conference on Parallel Processing"},{"journal-title":"Advanced Compiler Design and Implementation","year":"1997","author":"muchnik","key":"8"}],"event":{"name":"International Conference on Parallel Computing in Electrical Engineering","acronym":"PCEE-04","location":"Dresden, Germany"},"container-title":["Parallel Computing in Electrical Engineering, International Conference on"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9471\/30048\/01376733.pdf?arnumber=1376733","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T23:37:09Z","timestamp":1489448229000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1376733\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/pcee.2004.20","relation":{},"subject":[]}}