{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:29:10Z","timestamp":1729664950965,"version":"3.28.0"},"reference-count":48,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/pact.2011.71","type":"proceedings-article","created":{"date-parts":[[2012,1,6]],"date-time":"2012-01-06T14:28:47Z","timestamp":1325860127000},"page":"403-412","source":"Crossref","is-referenced-by-count":22,"title":["Memory Architecture for Integrating Emerging Memory Technologies"],"prefix":"10.1109","author":[{"given":"Kun","family":"Fang","sequence":"first","affiliation":[]},{"given":"Long","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Zhao","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Zhichun","family":"Zhu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","first-page":"301","article-title":"Reducing DRAM latencies with an integrated memory hierarchy design","author":"lin wei-fen","year":"2001","journal-title":"Proc 5th IEEE Symp High-Performance Computer Architecture"},{"key":"35","doi-asserted-by":"crossref","first-page":"45","DOI":"10.1145\/635508.605403","article-title":"Automatically characterizing large scale program behavior","volume":"36","author":"sherwood","year":"2002","journal-title":"Operating Systems Review (ACM)"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771791"},{"key":"36","doi-asserted-by":"crossref","first-page":"66","DOI":"10.1145\/511399.511343","article-title":"Symbiotic jobscheduling with priorities for a simultaneous multithreading processor","volume":"30","author":"snavely","year":"2002","journal-title":"Performance Evaluation Review"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555789"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/PESC.2004.1354830"},{"key":"15","first-page":"1","article-title":"Atlas: A scalable and high-performance scheduling algorithm for multiple memory controllers","author":"kim","year":"2010","journal-title":"Proc Int Symp High Performance Computer Architecture (HPCA)"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346206"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416650"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.1"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.21"},{"journal-title":"SPEC CPU2000 and CPU2006","year":"0","key":"37"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346190"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816012"},{"journal-title":"MetaRAM Product Brief","year":"0","key":"21"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1995.386537"},{"key":"43","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"journal-title":"Fully-Buffered DIMM Technology Moves Enterprise Platforms to the Next Level","year":"2005","author":"vogt","key":"42"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"journal-title":"Synopsys Design Compiler","year":"0","key":"40"},{"key":"48","first-page":"213","article-title":"A performance comparison of DRAM memory system optimizations for SMT processors","author":"zhu","year":"2005","journal-title":"Proceedings of the 11th International Symposium on High-Performance Computer Architecture"},{"key":"45","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"44","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1145\/360128.360134","article-title":"Permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality","author":"zhang zhao","year":"2000","journal-title":"Proceedings of the Annual International Symposium on Microarchitecture"},{"key":"47","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"46","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555788"},{"year":"2007","key":"22"},{"key":"23","article-title":"Operating system support for NVM+DRAM hybrid main memory","author":"mogul","year":"2009","journal-title":"Technical Report hpl-2009-256"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"25","first-page":"208","article-title":"Fair queuing CMP memory systems","author":"nesbit","year":"2006","journal-title":"Proc 29th Int l Symp Microarchitecture"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822773"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815981"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1126\/science.1110549"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654102"},{"journal-title":"On-chip MRAM As A High-bandwidth Low-latency Replacement for DRAM Physical Memories","year":"2002","author":"desikan","key":"10"},{"year":"0","key":"1"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232983"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"32","first-page":"128","article-title":"Memory access scheduling","author":"rixner","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815978"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854314"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379252"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744334"}],"event":{"name":"2011 International Conference on Parallel Architectures and Compilation Techniques (PACT)","start":{"date-parts":[[2011,10,10]]},"location":"Galveston, TX, USA","end":{"date-parts":[[2011,10,14]]}},"container-title":["2011 International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6112806\/6113772\/06113848.pdf?arnumber=6113848","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,25]],"date-time":"2021-12-25T04:53:09Z","timestamp":1640407989000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6113848\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":48,"URL":"https:\/\/doi.org\/10.1109\/pact.2011.71","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}