{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T23:43:04Z","timestamp":1729640584344,"version":"3.28.0"},"reference-count":72,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/pact.2011.21","type":"proceedings-article","created":{"date-parts":[[2012,1,6]],"date-time":"2012-01-06T19:28:47Z","timestamp":1325878127000},"page":"155-166","source":"Crossref","is-referenced-by-count":123,"title":["DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism"],"prefix":"10.1109","author":[{"given":"Byn","family":"Choi","sequence":"first","affiliation":[]},{"given":"Rakesh","family":"Komuravelli","sequence":"additional","affiliation":[]},{"given":"Hyojin","family":"Sung","sequence":"additional","affiliation":[]},{"given":"Robert","family":"Smolinski","sequence":"additional","affiliation":[]},{"given":"Nima","family":"Honarmand","sequence":"additional","affiliation":[]},{"given":"Sarita V.","family":"Adve","sequence":"additional","affiliation":[]},{"given":"Vikram S.","family":"Adve","sequence":"additional","affiliation":[]},{"given":"Nicholas P.","family":"Carter","sequence":"additional","affiliation":[]},{"given":"Ching-Tsun","family":"Chou","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"35","article-title":"Language overview","author":"gustafsson axum","year":"2009","journal-title":"Microsoft Language Specification"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669165"},{"key":"33","article-title":"Ct: A flexible parallel programming model for tera-scale architectures","author":"ghuloum","year":"2007","journal-title":"Intel White Paper"},{"journal-title":"Formal Specification and Verification of Sci Cache Coherence The Top Layers","year":"1989","author":"gjessing","key":"34"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1109\/IPPS.1997.580836"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555779"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195538"},{"journal-title":"The SCC Platform Overview","year":"0","key":"43"},{"key":"42","doi-asserted-by":"publisher","DOI":"10.1145\/1243418.1243424"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079450"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2007","author":"hennessy","key":"40"},{"key":"67","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749723"},{"key":"66","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.21"},{"key":"69","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/ISCA.1995.524546","article-title":"The SPLASH-2 programs: characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"68","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.50"},{"key":"22","article-title":"Multi-core implementations of the concurrent collections programming model","author":"budimlic","year":"2009","journal-title":"IWCPC"},{"key":"23","doi-asserted-by":"crossref","first-page":"246","DOI":"10.1145\/1080695.1069991","article-title":"Improving multiprocessor performance with Coarse-Grain Coherence Tracking","author":"cantin","year":"2005","journal-title":"Proceedings - International Symposium on Computer Architecture"},{"key":"24","article-title":"Efficient and flexible object sharing","author":"castro","year":"1995","journal-title":"Technical Report IST - INESC"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168893"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1145\/181181.181543"},{"key":"27","article-title":"Parallel SAH k-D tree construction","author":"choi","year":"2010","journal-title":"High Performance Graphics (HPG)"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1145\/1375634.1375649"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1992.276232"},{"key":"3","article-title":"So many states, so little time: Verifying memory coherence in the cray X1","author":"abts","year":"2003","journal-title":"IPDPS"},{"key":"2","article-title":"An evaluation of fine-grain producer-initiated communication in cache-coherent multiprocessors","author":"abdel-shafi","year":"1997","journal-title":"HPCA"},{"journal-title":"OpenSPARC? T2 System-on-chip (Soc) Microarchitecture Specification","year":"2008","key":"1"},{"journal-title":"Workshop on Deterministic Multiprocessing and Parallel Programming U-Washington","year":"2009","author":"adve","key":"7"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125941"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134502"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1996.501171"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134503"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1787234.1787255"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658652"},{"key":"70","article-title":"Verifying a multiprocessor cache controller using random case generation","volume":"7","author":"wood","year":"1990","journal-title":"IEEE DToC"},{"key":"71","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.14"},{"key":"9","doi-asserted-by":"crossref","first-page":"85","DOI":"10.1145\/1504176.1504190","article-title":"Serialization sets: A dynamic dependence-based parallel execution model","author":"allen","year":"2009","journal-title":"PPoPP"},{"key":"72","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669166"},{"key":"8","article-title":"Garnet: A detailed interconnection network model inside a full-system simulation framework","author":"agarwal","year":"2008","journal-title":"Technical Report CE-P08- 001 Princeton University"},{"key":"59","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.42"},{"key":"58","doi-asserted-by":"publisher","DOI":"10.1109\/71.113080"},{"key":"57","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.17"},{"key":"56","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset","volume":"33","author":"martin","year":"2005","journal-title":"SIGArch Computer Architecture News"},{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1994.288154"},{"key":"55","article-title":"Using destination-set prediction to improve the latency\/bandwidth tradeoff in shared-memory multiprocessors","author":"martin","year":"2003","journal-title":"ISCA"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2010.5649519"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1996.0107"},{"key":"15","article-title":"Midway: Shared memory parallel programming with entry consistency for distributed memory multiprocessors","author":"bershad","year":"1991","journal-title":"Technical Report TR CMU-CS-91-170 CMU"},{"journal-title":"Benchmarking Modern Multiprocessors","year":"2011","author":"bienia","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629579"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1640089.1640096"},{"key":"11","doi-asserted-by":"crossref","first-page":"320","DOI":"10.1109\/ISCA.1995.524572","article-title":"Empirical evaluation of the CRAY-T3D: a compiler perspective","author":"arpaci","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.42"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/1640089.1640097"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/1926385.1926447"},{"key":"64","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.38"},{"key":"65","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2002.1011412"},{"key":"62","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854331"},{"key":"63","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771778"},{"key":"60","article-title":"A formal specification and verification technique for cache coherence protocols","author":"nanda","year":"1992","journal-title":"ICPP"},{"key":"61","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508256"},{"key":"49","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250759"},{"key":"48","doi-asserted-by":"publisher","DOI":"10.1145\/224538.224569"},{"key":"45","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.82"},{"key":"44","doi-asserted-by":"crossref","first-page":"179","DOI":"10.1145\/209936.209955","article-title":"Reducing false sharing on shared memory multiprocessors through compile time data transformations","author":"jeremiassen","year":"1995","journal-title":"PPoPP"},{"key":"47","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555774"},{"key":"46","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1992.753300"},{"key":"10","doi-asserted-by":"crossref","first-page":"149","DOI":"10.1145\/1375581.1375600","article-title":"SharC: Checking data sharing strategies for multithreaded C","author":"anderson","year":"2008","journal-title":"PLDI"},{"key":"51","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1109\/ISCA.1995.524548","article-title":"Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors","author":"lebeck","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"52","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2006.180"},{"key":"53","article-title":"Conflict exceptions: Simplifying concurrent language semantics with precise hardware exceptions for data-races","author":"lucia","year":"2010","journal-title":"ISCA"},{"key":"54","doi-asserted-by":"publisher","DOI":"10.1145\/859639.859640"},{"key":"50","doi-asserted-by":"publisher","DOI":"10.1109\/SUPERC.1994.344313"}],"event":{"name":"2011 International Conference on Parallel Architectures and Compilation Techniques (PACT)","start":{"date-parts":[[2011,10,10]]},"location":"Galveston, TX, USA","end":{"date-parts":[[2011,10,14]]}},"container-title":["2011 International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6112806\/6113772\/06113797.pdf?arnumber=6113797","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,13]],"date-time":"2023-06-13T08:57:37Z","timestamp":1686646657000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6113797\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":72,"URL":"https:\/\/doi.org\/10.1109\/pact.2011.21","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}