{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:46:59Z","timestamp":1729655219750,"version":"3.28.0"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/micro.2014.36","type":"proceedings-article","created":{"date-parts":[[2015,1,21]],"date-time":"2015-01-21T14:34:11Z","timestamp":1421850851000},"page":"38-50","source":"Crossref","is-referenced-by-count":35,"title":["Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth"],"prefix":"10.1109","author":[{"given":"Nagendra","family":"Gulur","sequence":"first","affiliation":[]},{"given":"Mahesh","family":"Mehendale","sequence":"additional","affiliation":[]},{"given":"R.","family":"Manikantan","sequence":"additional","affiliation":[]},{"given":"R.","family":"Govindarajan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref11","first-page":"128","article-title":"Memory access scheduling","author":"rixner","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/358923.358939"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.31"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2009.5423920"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744366"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416628"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.45"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.30"},{"key":"ref27","doi-asserted-by":"crossref","first-page":"273","DOI":"10.1145\/313817.313948","article-title":"Way-predicting set-associative cache for high performance and low energy consumption","author":"inoue","year":"1999","journal-title":"Proceedings 1999 International Symposium on Low Power Electronics and Design (Cat No 99TH8477) LPE"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155673"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416642"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1996.501190"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485957"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628089"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/2.16187"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"ref9","first-page":"91","article-title":"Set-dueling-controlled adaptive insertion for highperformance caching","volume":"28","author":"qureshi","year":"2008","journal-title":"Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555801"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"416","DOI":"10.1145\/2508148.2485958","article-title":"Re-silient die-stacked DRAM caches","author":"sim","year":"2013","journal-title":"Proceedings of the 40th Annual International Symposium on Computer Architecture"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601880"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854333"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.42"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991105"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346202"}],"event":{"name":"2014 47th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","start":{"date-parts":[[2014,12,13]]},"location":"Cambridge, United Kingdom","end":{"date-parts":[[2014,12,17]]}},"container-title":["2014 47th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7008946\/7011360\/07011376.pdf?arnumber=7011376","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T00:03:14Z","timestamp":1498176194000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7011376\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/micro.2014.36","relation":{},"subject":[],"published":{"date-parts":[[2014,12]]}}}