{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T15:29:45Z","timestamp":1725809385392},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006,12]]},"DOI":"10.1109\/micro.2006.38","type":"proceedings-article","created":{"date-parts":[[2007,1,4]],"date-time":"2007-01-04T22:01:38Z","timestamp":1167948098000},"page":"433-442","source":"Crossref","is-referenced-by-count":31,"title":["Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions"],"prefix":"10.1109","author":[{"given":"Keshavan","family":"Varadarajan","sequence":"first","affiliation":[]},{"given":"S.K.","family":"Nandy","sequence":"additional","affiliation":[]},{"given":"Vishal","family":"Sharda","sequence":"additional","affiliation":[]},{"given":"Amrutur","family":"Bharadwaj","sequence":"additional","affiliation":[]},{"given":"Ravi","family":"Iyer","sequence":"additional","affiliation":[]},{"given":"Srihari","family":"Makineni","sequence":"additional","affiliation":[]},{"given":"Donald","family":"Newell","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/356887.356892"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1023\/B:SUPE.0000014800.27383.8f"},{"journal-title":"CACTI An Enhanced Cache Access and Cycle Time Model","year":"1996","author":"wilton","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086328"},{"key":"ref14","first-page":"336","article-title":"Victim replication: Maximizing capacity while hiding wire delay in tiled chip multiprocessors","author":"zhang","year":"2005","journal-title":"IEEE Computer Society"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(96)00123-3"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006246"},{"journal-title":"ecacti An enhanced power estimation model for on-chip caches Technical Report TR-04–28","year":"2004","author":"mamidipaka","key":"ref6"},{"key":"ref5","first-page":"111","article-title":"Fair cache sharing and partitioning in a chip multiprocessor architecture","author":"kim","year":"2004","journal-title":"IEEE Computer Society"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/371636.371687"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1095408.1095418"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.39"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253183"},{"journal-title":"SESC Simulator","year":"2005","author":"renau","key":"ref9"}],"event":{"name":"2006 39th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO'06)","start":{"date-parts":[[2006,12,9]]},"location":"Orlando, FL, USA","end":{"date-parts":[[2006,12,9]]}},"container-title":["2006 39th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO'06)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4041820\/4041821\/04041866.pdf?arnumber=4041866","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,15]],"date-time":"2017-03-15T21:00:51Z","timestamp":1489611651000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4041866\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/micro.2006.38","relation":{},"ISSN":["1072-4451"],"issn-type":[{"type":"print","value":"1072-4451"}],"subject":[],"published":{"date-parts":[[2006,12]]}}}