{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:59:21Z","timestamp":1729619961842,"version":"3.28.0"},"reference-count":35,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,11]]},"DOI":"10.1109\/memcod.2016.7797753","type":"proceedings-article","created":{"date-parts":[[2016,12,29]],"date-time":"2016-12-29T16:54:22Z","timestamp":1483030462000},"page":"105-114","source":"Crossref","is-referenced-by-count":4,"title":["Performance-aware scheduling of multicore time-critical systems"],"prefix":"10.1109","author":[{"given":"Jalil","family":"Boudjadar","sequence":"first","affiliation":[]},{"given":"Jin Hyun","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Simin","family":"Nadjm-Tehrani","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628104"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2500572"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DASC.2008.4702768"},{"key":"ref30","article-title":"Performance analysis and efficient execution on systems with multi-core CPUs, GPUs and MICs","author":"teodoro","year":"2015","journal-title":"CoRR abs\/1505 03819"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2012.32"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2015.24"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"397","DOI":"10.1007\/s10009-014-0361-y","article-title":"Uppaal SMC tutorial","volume":"17","author":"david","year":"2015","journal-title":"International Journal on Software Tools for Technology Transfer"},{"key":"ref11","first-page":"80","article-title":"Statistical model checking for networks of priced timed automata","volume":"6919","author":"david","year":"2011","journal-title":"FORMATS"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2011.5762713"},{"key":"ref13","article-title":"Coloured Petri net modelling of a generic avionics missions computer","author":"dodd","year":"2006","journal-title":"Technical Report Department of Defence Defence Science and Technology Organisation"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008186323068"},{"key":"ref15","first-page":"6b4-1","article-title":"Arinc 653 and multi-core microprocessors; considerations and potential impacts","author":"huyck","year":"2012","journal-title":"DASC'12"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925998"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2013.19"},{"key":"ref18","article-title":"Coordinated cache management for predictable multi-core real-time systems","author":"kim","year":"2014","journal-title":"Technical Report"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-45231-8_38"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522356"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1967677.1967696"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1851166.1851172"},{"key":"ref6","first-page":"69","article-title":"Compositional predictability analysis of mixed critical real time systems","author":"boudjadar","year":"2015","journal-title":"FTSCS'15"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/s10009-008-0095-9"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.scico.2015.10.003"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2012.26"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44618-4_12"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-60360-3_31"},{"key":"ref9","first-page":"31","article-title":"Multicore processor, parallelism and their performance analysis","volume":"2","author":"chhibber","year":"2014","journal-title":"IJARCS"},{"year":"2012","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSRE.2015.7381809"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2014.20"},{"key":"ref21","article-title":"Understanding shared memory bank access interference in multi-core avionics","author":"l\u00f6fwenmark","year":"2016","journal-title":"Proceedings of WCET'16 OpenAccess Series in Informatics (OASIcs)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MS.2005.102"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISORC.2011.36"},{"journal-title":"DO-297 Integrated Modular Avionics (IMA) Development Guidance and Certification Considerations","year":"2005","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"}],"event":{"name":"2016 ACM\/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","start":{"date-parts":[[2016,11,18]]},"location":"Kanpur, India","end":{"date-parts":[[2016,11,20]]}},"container-title":["2016 ACM\/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7786794\/7797738\/07797753.pdf?arnumber=7797753","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,16]],"date-time":"2019-09-16T22:15:39Z","timestamp":1568672139000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7797753\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,11]]},"references-count":35,"URL":"https:\/\/doi.org\/10.1109\/memcod.2016.7797753","relation":{},"subject":[],"published":{"date-parts":[[2016,11]]}}}