{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T07:21:08Z","timestamp":1725693668510},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2015,7,1]],"date-time":"2015-07-01T00:00:00Z","timestamp":1435708800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/jssc.2015.2411623","type":"journal-article","created":{"date-parts":[[2015,4,3]],"date-time":"2015-04-03T20:43:54Z","timestamp":1428093834000},"page":"1669-1679","source":"Crossref","is-referenced-by-count":42,"title":["A Programmable Frequency Multiplier-by-29 Architecture for Millimeter Wave Applications"],"prefix":"10.1109","volume":"50","author":[{"given":"Clement","family":"Jany","sequence":"first","affiliation":[]},{"given":"Alexandre","family":"Siligaris","sequence":"additional","affiliation":[]},{"given":"Jose Luis","family":"Gonzalez-Jimenez","sequence":"additional","affiliation":[]},{"given":"Pierre","family":"Vincent","sequence":"additional","affiliation":[]},{"given":"Philippe","family":"Ferrari","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2320952"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2011.6026605"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1934.226781"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2014.6908522"},{"key":"ref37","first-page":"366","article-title":"21.4 A 42 mW 230 fs-jitter sub-sampling 60 GHz PLL in 40 nm CMOS","author":"szortyka","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"1629","DOI":"10.1109\/TMTT.2009.2021833","article-title":"A phase-locked loop with injection-locked frequency multiplier in 0.18-$\\mu$<\/tex><\/formula>m CMOS for V-band applications","volume":"57","author":"wu","year":"2009","journal-title":"IEEE Trans Microw Theory Tech"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746232"},{"key":"ref34","year":"0"},{"key":"ref10","first-page":"352","article-title":"A 56.4-to-63.4 GHz spurious-free all-digital fractional-N PLL in 65 nm CMOS","author":"wanghua","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"1446","DOI":"10.1109\/JSSC.2004.831598","article-title":"A 700-kHz bandwidth $\\Sigma \\Delta$<\/tex><\/formula> fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications","volume":"39","author":"temporiti","year":"2004","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405750"},{"key":"ref13","article-title":"A 2.3 GHz fractional-N dividerless phase-locked loop with ${-}$<\/tex> <\/formula>112 dBc\/Hz in-band phase noise","author":"huang","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2161500"},{"key":"ref15","first-page":"192","article-title":"An 8.5 mW, 0.07 mm$^2$<\/tex><\/formula> ADPLL in 28 nm CMOS with sub-ps resolution TDC and ${<} $<\/tex><\/formula>230 fs RMS jitter","author":"shen","year":"2013","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280832"},{"key":"ref17","first-page":"88","article-title":"A 2.9-to-4.0 GHz fractional-N digital PLL with bang-bang phase detector and 560 fs rms integrated jitter at 4.5 mW power","author":"tasca","year":"2011","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref19","first-page":"110","article-title":"A low spur fractional-N digital PLL for 802.11 a\/b\/g\/n\/ac with 0.19 psrms jitter","author":"yao","year":"2011","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942113"},{"key":"ref4","year":"0"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977524"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2166184"},{"key":"ref6","first-page":"262","article-title":"A 9% power efficiency 121-to-137 GHz phasecontrolled push-push frequency quadrupler in 0.13 $\\mu$<\/tex><\/formula>m SiGe BiCMOS","author":"wang","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MWSYM.2014.6848301"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/PIMRC.1997.631039"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005702"},{"key":"ref7","article-title":"A 56-to-65 GHz injection-locked frequency tripler with quadrature outputs in 90 nm CMOS","author":"chan","year":"2008","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref2","first-page":"422","article-title":"A 13.1% tuning range 115 GHz frequency generator based on an injection-locked frequency doubler in 65 nm CMOS","author":"mazzanti","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433941"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2166336"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405750"},{"key":"ref22","first-page":"176","article-title":"An integral path self-calibration scheme for a 20.1?26.7 GHz dual-loop PLL in 32 nm SOI CMOS","author":"feriss","year":"2012","journal-title":"Symp VLSI Dig Tech Papers"},{"key":"ref21","first-page":"196","article-title":"A 25 GHz 100 ns lock time digital LC PLL with an 8-phase output clock","author":"navid","year":"2013","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.922395"},{"key":"ref23","first-page":"198","article-title":"A 28 GHz hybrid PLL in 32 nm SOI CMOS","author":"ferriss","year":"2013","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320940"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2149610"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7131594\/07079534.pdf?arnumber=7079534","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:47:24Z","timestamp":1642006044000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7079534\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":37,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2015.2411623","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,7]]}}}