{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,10]],"date-time":"2024-06-10T21:53:27Z","timestamp":1718056407452},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/jssc.2014.2369503","type":"journal-article","created":{"date-parts":[[2014,12,11]],"date-time":"2014-12-11T19:46:11Z","timestamp":1418327171000},"page":"125-136","source":"Crossref","is-referenced-by-count":42,"title":["A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking"],"prefix":"10.1109","volume":"50","author":[{"given":"Edith","family":"Beigne","sequence":"first","affiliation":[]},{"given":"Alexandre","family":"Valentian","sequence":"additional","affiliation":[]},{"given":"Ivan","family":"Miro-Panades","sequence":"additional","affiliation":[]},{"given":"Robin","family":"Wilson","sequence":"additional","affiliation":[]},{"given":"Philippe","family":"Flatresse","sequence":"additional","affiliation":[]},{"given":"Fady","family":"Abouzeid","sequence":"additional","affiliation":[]},{"given":"Thomas","family":"Benoist","sequence":"additional","affiliation":[]},{"given":"Christian","family":"Bernard","sequence":"additional","affiliation":[]},{"given":"Sebastien","family":"Bernard","sequence":"additional","affiliation":[]},{"given":"Olivier","family":"Billoint","sequence":"additional","affiliation":[]},{"given":"Sylvain","family":"Clerc","sequence":"additional","affiliation":[]},{"given":"Bastien","family":"Giraud","sequence":"additional","affiliation":[]},{"given":"Anuj","family":"Grover","sequence":"additional","affiliation":[]},{"given":"Julien","family":"Le Coz","sequence":"additional","affiliation":[]},{"given":"Jean-Philippe","family":"Noel","sequence":"additional","affiliation":[]},{"given":"Olivier","family":"Thomas","sequence":"additional","affiliation":[]},{"given":"Yvain","family":"Thonnart","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523226"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2011.5783192"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6478970"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.826192"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177100"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2001.955087"},{"key":"ref4","first-page":"178","article-title":"A 280 mV-to-1.1 V 256 b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22 nm CMOS","author":"hsu","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","first-page":"66","article-title":"A 280 mV-to-1.2 V wide-operating-range IA-32 processor in 32 nm CMOS","author":"jain","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref6","first-page":"153","article-title":"28 nm CMOS, energy efficient and variability tolerant, 350 mV-to-1.0 V, 10 MHz\/700 MHz, 252 bits frame error-decoder","author":"abouzeid","year":"2012","journal-title":"Proc ESSCIRC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594288"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2273844"},{"key":"ref7","article-title":"Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors","author":"tschanz","year":"2001","journal-title":"Int Symp Low Power Electronics and Design (ISLPED)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746251"},{"key":"ref1","first-page":"44c","article-title":"2.6 GHZ ultra wide voltage range energy efficient dual A9 in 28 nm UTBB FD-SOI","author":"jacquet","year":"2013","journal-title":"VLSI Technology (VLSIT)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6998099\/06982238.pdf?arnumber=6982238","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:27:49Z","timestamp":1642004869000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6982238\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":15,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2369503","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,1]]}}}