{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T07:51:25Z","timestamp":1725436285289},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2014,6,1]],"date-time":"2014-06-01T00:00:00Z","timestamp":1401580800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/jssc.2014.2322868","type":"journal-article","created":{"date-parts":[[2014,5,19]],"date-time":"2014-05-19T18:04:17Z","timestamp":1400522657000},"page":"1437-1447","source":"Crossref","is-referenced-by-count":130,"title":["A Low-Noise Design Technique for High-Speed CMOS Optical Receivers"],"prefix":"10.1109","volume":"49","author":[{"given":"Dan","family":"Li","sequence":"first","affiliation":[]},{"given":"Gabriele","family":"Minoia","sequence":"additional","affiliation":[]},{"given":"Matteo","family":"Repossi","sequence":"additional","affiliation":[]},{"given":"Daniele","family":"Baldi","sequence":"additional","affiliation":[]},{"given":"Enrico","family":"Temporiti","sequence":"additional","affiliation":[]},{"given":"Andrea","family":"Mazzanti","sequence":"additional","affiliation":[]},{"given":"Francesco","family":"Svelto","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"120","article-title":"100 Gb\/s Ethernet chipsets in 65 nm CMOS technology","author":"jiang","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052255"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1002\/0471726400"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.918914"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.833547"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"2945","DOI":"10.1109\/JSSC.2006.884388","article-title":"A fully integrated 20-Gb\/s optoelectronic transceiver implemented in a standard 0.13- $\\mu\\hbox{m}$<\/tex><\/ref_formula> CMOS SOI technology","volume":"41","author":"analui","year":"2006","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref16","first-page":"221","article-title":"A 25 Gb\/s low noise 65 nm CMOS receiver tailored to 100GBASE-LR4","author":"li","year":"2012","journal-title":"IEEE Proc ESSCIRC"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.826816"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2178723"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.875301"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034444"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-009-5115-4"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2012.6146487"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2020712"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2189835"},{"key":"ref7","year":"2010","journal-title":"IEEE 802 3ba Standard"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2014298"},{"key":"ref1","year":"2012","journal-title":"?IEEE 802 3 BWA Ad Hoc Report ?"},{"key":"ref9","first-page":"118","article-title":"A 4 $\\times$<\/tex><\/ref_formula> 25-to-28 Gb\/s 4.9 mW\/Gb\/s $-$<\/tex><\/ref_formula>9.7 dBm high-sensitivity optical receiver based on 65 nm CMOS for board-to-board interconnects","author":"takemoto","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"2138","DOI":"10.1109\/JSSC.2003.818567","article-title":"10-Gb\/s limiting amplifier and laser\/modulator driver in 0.18- $\\mu\\hbox{m}$<\/tex> <\/ref_formula> CMOS technology","volume":"38","author":"galal","year":"2003","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref22","first-page":"418","article-title":"25 Gb\/s 3.6 pJ\/b and 15 Gb\/s 1.37 pJ\/b VCSEL-based optical links in 90 nm CMOS","author":"proesel","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref21","first-page":"341","article-title":"InP DHBT transimpedance amplifiers with automatic offset compensation for 100 Gbit\/s optical communications","author":"dupuy","year":"2010","journal-title":"Proc EUMIC"},{"key":"ref24","first-page":"116","article-title":"A quad 25 Gb\/s 270 mW TIA in 0.13 $\\mu\\hbox{m}$<\/tex><\/ref_formula> BiCMOS with $<$<\/tex><\/ref_formula>0.15 dB crosstalk penalty","author":"kalogerakis","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2245059"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6822663\/06818448.pdf?arnumber=6818448","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:56:16Z","timestamp":1642006576000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6818448"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":24,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2322868","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,6]]}}}