{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,31]],"date-time":"2024-08-31T05:07:25Z","timestamp":1725080845730},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2013,3,1]],"date-time":"2013-03-01T00:00:00Z","timestamp":1362096000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2013,3]]},"DOI":"10.1109\/jssc.2012.2235013","type":"journal-article","created":{"date-parts":[[2013,1,8]],"date-time":"2013-01-08T22:13:07Z","timestamp":1357683187000},"page":"864-877","source":"Crossref","is-referenced-by-count":85,"title":["An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory"],"prefix":"10.1109","volume":"48","author":[{"given":"Meng-Fan","family":"Chang","sequence":"first","affiliation":[]},{"given":"Shin-Jang","family":"Shen","sequence":"additional","affiliation":[]},{"given":"Chia-Chi","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Che-Wei","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Yu-Fan","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Ya-Chin","family":"King","sequence":"additional","affiliation":[]},{"given":"Chorng-Jung","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Hung-Jen","family":"Liao","sequence":"additional","affiliation":[]},{"given":"Yu-Der","family":"Chih","sequence":"additional","affiliation":[]},{"given":"Hiroyuki","family":"Yamauchi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"30","article-title":"A 1.25 um $^{2}$<\/tex><\/formula> cell 32 Kb electrical fuse memory in 32 nm CMOS with 700 mV Vddmin and parallel\/serial interface","author":"chung","year":"2009","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref38","first-page":"406","article-title":"A commercial field-programmable dense eFUSE array memory with 99.999% sense yield for 45 nm SOI CMOS","author":"uhlmann","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref33","first-page":"242","article-title":"A 113 mm $^2$<\/tex><\/formula> 32 Gb 3b\/cell NAND flash memory","author":"futatsuyama","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.811704"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.840985"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013763"},{"key":"ref37","first-page":"28","article-title":"High-density 3-D metal-fuse PROM featuring 1.37 $\\mu$<\/tex> <\/formula>m$^{2}$<\/tex> <\/formula> 1T1R bit cell in 32 nm high-k metal-gate CMOS technology","author":"kulkarni","year":"2009","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref36","first-page":"206","article-title":"An offset tolerant current-sampling-based sense amplifier for sub-100 nA-cell-current nonvolatile memory","author":"chang","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref35","first-page":"424","article-title":"A 45 nm self-aligned-contact process 1 Gb NOR flash with 5 MB\/s program speed","author":"javanifard","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007154"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332709"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672110"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2060279"},{"key":"ref13","first-page":"434","article-title":"A 0.5 V 4 Mb logic-process compatible embedded resistive RAM (ReRAM) in 65 nm CMOS using low voltage current-mode sensing scheme with 45 ns random read time","author":"chang","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","first-page":"266","article-title":"A 0.29 V embedded NAND-ROM in 90 nm CMOS for ultra-low-voltage applications","author":"chang","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"837","DOI":"10.1109\/LED.2007.903953","article-title":"A 0.26-mm $^2$<\/tex><\/formula> U-shaped nitride-based programming cell on pure 90-nm CMOS technology","volume":"28","author":"lai","year":"2007","journal-title":"IEEE Electron Device Lett"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418871"},{"key":"ref17","first-page":"2592","article-title":"A 256 kb subthreshold SRAM in 65 nm CMOS","author":"calhoun","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020201"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001903"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"877","DOI":"10.1109\/JSSC.2005.845564","article-title":"A 130-nm 0.9 V 66-MHz 8-Mb (256 K$\\times\\,$<\/tex> <\/formula>32) local SONOS embedded flash EEPROM","volume":"40","author":"seo","year":"2005","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref4","first-page":"240","article-title":"A 48 nm 32 Gb 8-level NAND flash memory with 5.5 MBs program throughput","author":"chang","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref27","first-page":"74","article-title":"A 512$\\times\\,$<\/tex><\/formula>8 electrical fuse memory with 15 $\\mu$<\/tex><\/formula>m2 cells using 8-sq asymmetric fuse and core devices in 90 nm CMOS","author":"chung","year":"2007","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493861"},{"key":"ref6","first-page":"198","article-title":"A 151 mm $^{2}$<\/tex><\/formula> 64 Gb MLC NAND flash memory in 24 nm CMOS technology","author":"fukuda","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.883319"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433949"},{"key":"ref8","first-page":"436","article-title":"128 Gb 3b\/cell NAND flash memory in 19 nm technology with 18 MB\/s write rate and 400 Mb\/s toggle mode","author":"li","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","first-page":"430","article-title":"A 64 Gb 533 Mb\/s DDR interface MLC NAND flash in sub-20 nm technology","author":"lee","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","first-page":"507","article-title":"A 56-nm CMOS 99-nm$^2$<\/tex><\/formula> 8-Gb multi-level NAND flash memory with 10 MB\/s program throughput","author":"takeuchi","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","first-page":"260","article-title":"A 0.13 $\\mu$<\/tex><\/formula>m 64 Mb multi-layered conductive metal-oxide memory","author":"chevallier","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"186","DOI":"10.1109\/JSSC.2008.2007152","article-title":"A 34 MB\/s MLC write throughput 16 Gb NAND with all bit line architecture on 56 nm technology","volume":"44","author":"cernea","year":"2009","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011972"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.881549"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342741"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/4.871317"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/4.568831"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006439"},{"key":"ref25","first-page":"472","article-title":"A 90 nm 1.8 V 512 Mb diode-switch PRAM with 266 MB\/s read throughput","author":"lee","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/6466407\/06407149.pdf?arnumber=6407149","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:38Z","timestamp":1638217718000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6407149\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":39,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2012.2235013","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,3]]}}}