{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,3,3]],"date-time":"2024-03-03T10:57:20Z","timestamp":1709463440058},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2010,12,1]],"date-time":"2010-12-01T00:00:00Z","timestamp":1291161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1109\/jssc.2010.2077370","type":"journal-article","created":{"date-parts":[[2010,10,19]],"date-time":"2010-10-19T18:36:31Z","timestamp":1287513391000},"page":"2723-2736","source":"Crossref","is-referenced-by-count":89,"title":["A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation"],"prefix":"10.1109","volume":"45","author":[{"given":"Enrico","family":"Temporiti","sequence":"first","affiliation":[]},{"given":"Colin","family":"Weltin-Wu","sequence":"additional","affiliation":[]},{"given":"Daniele","family":"Baldi","sequence":"additional","affiliation":[]},{"given":"Marco","family":"Cusmai","sequence":"additional","affiliation":[]},{"given":"Francesco","family":"Svelto","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/18.256489"},{"key":"ref11","first-page":"355","article-title":"quantization and dither: a theoretical survey","volume":"40","author":"lipshitz","year":"1992","journal-title":"J Audio Eng Soc"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DCAS.2006.321040"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPAA.1993.379977"},{"key":"ref14","first-page":"352","article-title":"a 14 mw fractional-$n$<\/tex><\/formula> pll modulator with an enhanced digital phase detector and frequency switching scheme","author":"ferriss","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/4.823449"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"768","DOI":"10.1109\/JSSC.2010.2040232","article-title":"A fractional-$N$<\/tex> <\/formula> PLL for multiband (0.8–6 GHz) communications using binary-weighted D\/A differentiator and offset-frequency $\\Delta\\hbox{-}\\Sigma$<\/tex><\/formula> modulator","volume":"45","author":"jian","year":"2010","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2012363"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2028753"},{"key":"ref6","first-page":"476","article-title":"a 3 mhz-bw 3.6 ghz digital fractional-$n$<\/tex><\/formula> pll with sub-gate-delay tdc, phase-interpolation divider and digital mismatch cancellation","author":"zanuso","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2077370"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/0029-554X(63)90314-8"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"2787","DOI":"10.1109\/JSSC.2008.2005716","article-title":"spurious tone suppression techniques applied to a wide-bandwidth 2.4 ghz fractional- $n$<\/tex><\/formula> pll","volume":"43","author":"wang","year":"2008","journal-title":"IEEE Journal of Solid-State Circuit"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"2776","DOI":"10.1109\/JSSC.2008.2005704","article-title":"a low-noise wide-bw 3.6-ghz digital $\\delta\\sigma$<\/tex> <\/formula> fractional-$n$<\/tex> <\/formula> frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation","volume":"43","author":"hsu","year":"2008","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DCAS.2009.5505727"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5625049\/05604330.pdf?arnumber=5604330","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:45:44Z","timestamp":1633913144000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5604330\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":16,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2010.2077370","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,12]]}}}