{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T17:21:11Z","timestamp":1694625671616},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2006,4,1]],"date-time":"2006-04-01T00:00:00Z","timestamp":1143849600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2006,4]]},"DOI":"10.1109\/jssc.2006.870924","type":"journal-article","created":{"date-parts":[[2006,4,7]],"date-time":"2006-04-07T00:18:08Z","timestamp":1144369088000},"page":"759-771","source":"Crossref","is-referenced-by-count":35,"title":["A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a CELL Processor"],"prefix":"10.1109","volume":"41","author":[{"given":"H.-J.","family":"Oh","sequence":"first","affiliation":[]},{"given":"S.M.","family":"Mueller","sequence":"additional","affiliation":[]},{"given":"C.","family":"Jacobi","sequence":"additional","affiliation":[]},{"given":"B.W.","family":"Michael","sequence":"additional","affiliation":[]},{"given":"H.","family":"Nishikawa","sequence":"additional","affiliation":[]},{"given":"Y.","family":"Totsuka","sequence":"additional","affiliation":[]},{"given":"T.","family":"Namatame","sequence":"additional","affiliation":[]},{"given":"N.","family":"Yano","sequence":"additional","affiliation":[]},{"given":"T.","family":"Machida","sequence":"additional","affiliation":[]},{"given":"S.H.","family":"Dhong","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/12.485568"},{"key":"ref11","author":"ercegovac","year":"2004","journal-title":"Digital Arithmetic"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-04267-0"},{"key":"ref13","author":"parhami","year":"2000","journal-title":"Computer Arithmetic Algorithms and Hardware Design"},{"key":"ref14","author":"weste","year":"1985","journal-title":"Principles of CMOS VLSI Design A System Perspective"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.97"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1145\/545214.545218","article-title":"the optimal logic depth per pipeline stage is 6 to 8 fo4 inverter delays","author":"hrishikesh","year":"2002","journal-title":"Proc 29th Int Symp Computer Architecture (ISCA-29)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2005.1469324"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332597"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.46"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2005.45"},{"key":"ref7","author":"koren","year":"2002","journal-title":"Computer Arithmetic Algorithms"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493930"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493905"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870924"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/33823\/01610620.pdf?arnumber=1610620","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:06Z","timestamp":1638217686000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1610620\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,4]]},"references-count":15,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2006,4]]}},"URL":"https:\/\/doi.org\/10.1109\/jssc.2006.870924","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[2006,4]]}}}