{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T17:07:28Z","timestamp":1725469648752},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/ivsw.2017.8031555","type":"proceedings-article","created":{"date-parts":[[2017,9,14]],"date-time":"2017-09-14T20:47:18Z","timestamp":1505422038000},"page":"111-116","source":"Crossref","is-referenced-by-count":1,"title":["Asserting causal properties in High Level Synthesis"],"prefix":"10.1109","author":[{"given":"Erwan","family":"Fabiani","sequence":"first","affiliation":[]},{"given":"Loic","family":"Lagadec","sequence":"additional","affiliation":[]},{"given":"Mohamed Ben","family":"Hammouda","sequence":"additional","affiliation":[]},{"given":"Ciprian","family":"Teodorov","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Open Verification Library Assertion Monitor Reference Manual","year":"2009","key":"ref4"},{"journal-title":"Accellera System Verilog 3 1 Language Reference Manual","year":"2001","key":"ref3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865091"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2006.319966"},{"key":"ref11","first-page":"1","article-title":"Assertion support in high-level synthesis design flow","author":"ribon","year":"2011","journal-title":"FDL 2011 Proceedings"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-1125-9_8"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8588-8_9"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.69"},{"journal-title":"High-Level Synthesis Introduction to Chip and System Design","year":"1992","author":"gajski","key":"ref7"},{"journal-title":"Property Specification Language Reference Manual Version 1 1","year":"2004","key":"ref2"},{"journal-title":"Codeveloper User Guide Impulse Accelerated Technologies","year":"2015","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2009.5351246"}],"event":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","start":{"date-parts":[[2017,7,3]]},"location":"Thessaloniki, Greece","end":{"date-parts":[[2017,7,5]]}},"container-title":["2017 IEEE 2nd International Verification and Security Workshop (IVSW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8024489\/8031534\/08031555.pdf?arnumber=8031555","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,10,3]],"date-time":"2017-10-03T02:58:10Z","timestamp":1506999490000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8031555\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ivsw.2017.8031555","relation":{},"subject":[],"published":{"date-parts":[[2017,7]]}}}