{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T21:23:02Z","timestamp":1725657782056},"reference-count":17,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,4,5]],"date-time":"2023-04-05T00:00:00Z","timestamp":1680652800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,5]],"date-time":"2023-04-05T00:00:00Z","timestamp":1680652800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,4,5]]},"DOI":"10.1109\/isqed57927.2023.10129356","type":"proceedings-article","created":{"date-parts":[[2023,5,24]],"date-time":"2023-05-24T17:33:09Z","timestamp":1684949589000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["H-Saber: An FPGA-Optimized Version for Designing Fast and Efficient Post-Quantum Cryptography Hardware Accelerators"],"prefix":"10.1109","author":[{"given":"Andrea","family":"Guerrieri","sequence":"first","affiliation":[{"name":"University of Applied Sciences and Arts Western Switzerland,Geneva,Switzerland"}]},{"given":"Gabriel","family":"Da Silva Marques","sequence":"additional","affiliation":[{"name":"University of Applied Sciences and Arts Western Switzerland,Geneva,Switzerland"}]},{"given":"Francesco","family":"Regazzoni","sequence":"additional","affiliation":[{"name":"Università Della Svizzera Italiana,Lugano,Switzerland"}]},{"given":"Andres","family":"Upegui","sequence":"additional","affiliation":[{"name":"University of Applied Sciences and Arts Western Switzerland,Geneva,Switzerland"}]}],"member":"263","reference":[{"key":"ref13","first-page":"361","article-title":"Opti-mizing post-quantum cryptography codes for high-level synthesis","author":"guerrieri","year":"2022","journal-title":"2022 Euromicro Conference on digital systems Design (DSD22)"},{"key":"ref12","article-title":"Parallel Programming for FPGAs","author":"kastner","year":"2018","journal-title":"ArXiv e-prints"},{"journal-title":"IEEE Solid-State Circuits Society","article-title":"Post-Quantum Cryptography: A New Cybersecurity Era: Presented by Joppe Bos","year":"0","key":"ref15"},{"journal-title":"PQC standardization process Announcing four candidates to be standardized plus fourth round candidates","year":"2022","key":"ref14"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-020-9414-8"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"ref2","first-page":"1","article-title":"Comparing energy efficiency of cpu, gpu and fpga implementations for vision kernels","author":"qasaimeh","year":"2019","journal-title":"2019 IEEE International Conference on Embedded Software and Systems (ICESS) ICESS"},{"journal-title":"Guidelines for Submitting Tweaks for Third Round Finalists and Candidates","year":"2020","key":"ref1"},{"article-title":"Hardware api for post-quantum public key cryptosystems","year":"0","author":"ferozpuri","key":"ref17"},{"journal-title":"SABER Mod-LWR based KEM (Round 2 Submission)","year":"2020","key":"ref16"},{"key":"ref8","first-page":"1","article-title":"Inter-procedural resource sharing in high level synthesis through function proxies","author":"minutoli","year":"2016","journal-title":"Proceedings of the International Conference on Field Programmable Logic and Applications"},{"article-title":"Transformations of high-level synthesis codes for high-performance computing","year":"2018","author":"licht","key":"ref7"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2017.8335152"},{"key":"ref4","first-page":"361","article-title":"Compact domain-specific co-processor for accelerating module lattice-based key encapsulation mechanism","author":"jose maria","year":"2020","journal-title":"In 57th Design and Automation Conference DAC 2020"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2834439"},{"key":"ref6","first-page":"361","article-title":"High-speed instruction-set coprocessor for lattice-based key encapsulation mechanism: Saber in hardware","author":"roy","year":"2020","journal-title":"IACR Transactions on Cryptographic Hardware and Embedded Systems 2020"},{"key":"ref5","first-page":"361","article-title":"Implementing and benchmarking three lattice-based post-quantum cryptography algorithms using software\/hardware codesign","author":"dang","year":"2000","journal-title":"2019 International Conference on Field-Programmable Technology (ICFPT)"}],"event":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2023,4,5]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2023,4,7]]}},"container-title":["2023 24th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10129281\/10129282\/10129356.pdf?arnumber=10129356","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,12]],"date-time":"2023-06-12T17:55:07Z","timestamp":1686592507000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10129356\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4,5]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/isqed57927.2023.10129356","relation":{},"subject":[],"published":{"date-parts":[[2023,4,5]]}}}