{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T01:40:51Z","timestamp":1729647651526,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,3]]},"DOI":"10.1109\/isqed.2009.4810326","type":"proceedings-article","created":{"date-parts":[[2009,4,3]],"date-time":"2009-04-03T14:50:11Z","timestamp":1238770211000},"page":"388-393","source":"Crossref","is-referenced-by-count":3,"title":["A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations"],"prefix":"10.1109","author":[{"given":"Koustav","family":"Bhattacharya","sequence":"first","affiliation":[]},{"given":"Nagarajan","family":"Ranganathan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/368640.368665"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1999.759786"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393948"},{"key":"15","article-title":"time redundancy based scan flip-flop reuse to reduce ser ofcombinational logic","volume":"617 624","author":"elakkumanan","year":"2006","journal-title":"Proc ofISQED"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466156"},{"key":"13","doi-asserted-by":"crossref","first-page":"155","DOI":"10.1109\/TCAD.2005.853696","article-title":"gate sizing to radiation harden combinational logic","volume":"25","author":"zhou","year":"2006","journal-title":"Trans CAD"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382535"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012594"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271075"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560212"},{"journal-title":"Trans on Design and Test 362-375","article-title":"soft-spot analysis: targeting compound noise effects in nanometer circuits","year":"2005","author":"zhao","key":"20"},{"year":"0","key":"2"},{"journal-title":"85 benchmark circuits","year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.143"},{"key":"6","first-page":"309","article-title":"an efficient algorithm for statistical minimization of total power under timing yield constraints","author":"mani","year":"2005","journal-title":"Proc ofDAC"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332385"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379043"},{"key":"9","doi-asserted-by":"crossref","first-page":"1621","DOI":"10.1109\/43.248073","article-title":"an exact solution to the transistor sizing problem for cmos circuits using convex optimization","volume":"12","author":"sapatnekar","year":"1993","journal-title":"Trans CAD"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233603"}],"event":{"name":"2009 10th International Symposium on Quality of Electronic Design (ISQED)","start":{"date-parts":[[2009,3,16]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2009,3,18]]}},"container-title":["2009 10th International Symposium on Quality of Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4804412\/4810250\/04810326.pdf?arnumber=4810326","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T14:34:33Z","timestamp":1497796473000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4810326\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,3]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/isqed.2009.4810326","relation":{},"subject":[],"published":{"date-parts":[[2009,3]]}}}