{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:14:14Z","timestamp":1729642454371,"version":"3.28.0"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,5]]},"DOI":"10.1109\/isorc.2018.00024","type":"proceedings-article","created":{"date-parts":[[2018,8,20]],"date-time":"2018-08-20T18:52:15Z","timestamp":1534791135000},"page":"116-123","source":"Crossref","is-referenced-by-count":0,"title":["A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems"],"prefix":"10.1109","author":[{"given":"Mohammad Shihabul","family":"Haque","sequence":"first","affiliation":[]},{"given":"Sriram","family":"Vasudevan","sequence":"additional","affiliation":[]},{"given":"Alamuri Sriram","family":"Nihar","sequence":"additional","affiliation":[]},{"given":"Arvind","family":"Easwaran","sequence":"additional","affiliation":[]},{"given":"Akash","family":"Kumar","sequence":"additional","affiliation":[]},{"given":"Y.C.","family":"Tay","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Designing A Dynamically Reconfigurable Cache for High Performance and Low Power","year":"2002","author":"spanberger","key":"ref10"},{"key":"ref11","article-title":"Dyrectape: a dynamically reconfigurable cache using domain wall memory tapes","author":"ranjan","year":"0","journal-title":"DATE'15"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/NAS.2013.11"},{"key":"ref13","article-title":"The V-Way cache: demand-based associativity via global replacement","author":"qureshi","year":"0","journal-title":"ISCA'05"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.20"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2012.6404160"},{"key":"ref16","article-title":"Adaptive line placement with the set balancing cache","author":"rol\u00e1n","year":"0","journal-title":"Micro'09"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/291006.291053"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2006.1639487"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"544","DOI":"10.1109\/ISCA.2005.52","article-title":"The v-way cache: Demand based associativity via global replacement","author":"qureshi","year":"2005","journal-title":"Proc 32nd International Symp on Computer Architecture"},{"journal-title":"Vivado simulator","year":"2016","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/92.931228"},{"journal-title":"Performance Analysis Guide for Intel Core I7 Processor and Intel Xeon 5500 Processors","year":"2008","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339685"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2008.46"},{"journal-title":"Arm cortex –a series programmer's guide for ARMv8 – A","year":"2016","key":"ref29"},{"key":"ref5","first-page":"1","article-title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","author":"ho","year":"2015","journal-title":"Proc 2015 NASA\/ESA Conf Adaptive Hardware and Systems (AHS)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165153"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CAST.2016.7914987"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2339819"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-013-0291-4"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2613933"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.20"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1186736.1186737","article-title":"Spec cpu2006 benchmark descriptions","volume":"34","author":"henning","year":"2006","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/986537.986601"},{"key":"ref24","article-title":"The new linux perf tools","volume":"18","author":"de melo","year":"2010","journal-title":"Slides from Linux Kongress"},{"journal-title":"Memory characterization of workloads using instrumentation driven simulation a pin based memory characterization of the spec cpu 2000 and spec cpu 2006 benchmark suites","year":"2007","author":"jaleel","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1629435.1629476"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"}],"event":{"name":"2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC)","start":{"date-parts":[[2018,5,29]]},"location":"Singapore","end":{"date-parts":[[2018,5,31]]}},"container-title":["2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8419659\/8421131\/08421155.pdf?arnumber=8421155","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,7]],"date-time":"2020-11-07T20:40:46Z","timestamp":1604781646000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8421155\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/isorc.2018.00024","relation":{},"subject":[],"published":{"date-parts":[[2018,5]]}}}