{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T16:48:20Z","timestamp":1729615700451,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.1999.777794","type":"proceedings-article","created":{"date-parts":[[2003,1,20]],"date-time":"2003-01-20T12:23:24Z","timestamp":1043065404000},"page":"13-18","source":"Crossref","is-referenced-by-count":0,"title":["Synthesis of checker EFSMs from timing diagram specifications"],"prefix":"10.1109","volume":"1","author":[{"given":"E.K.","family":"Ogoubi","sequence":"first","affiliation":[]},{"given":"E.","family":"Cerny","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.479877"},{"journal-title":"FMCAD'96","article-title":"Validity Checking for Combinations of Theories with Equality","year":"1996","author":"barrett","key":"ref11"},{"journal-title":"Real-Time Object-Oriented Modeling","year":"1994","author":"selic","key":"ref12"},{"journal-title":"Verilog Digital Computer Design Algorithms Into Hardware","year":"1999","author":"arnold","key":"ref13"},{"volume":"1","journal-title":"Practical Methods for Hardware Design Research Reports","year":"1997","key":"ref14"},{"journal-title":"The VHDL Hardware Description Language","year":"0","key":"ref15"},{"journal-title":"PCI System Architecture","year":"1997","author":"shanley","key":"ref16"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-63475-4","volume":"1287","author":"kropf","year":"1997","journal-title":"Lecture Notes in Computer Science"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-2007-4_2"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/BF00243132"},{"journal-title":"Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method","year":"1998","author":"cerny","key":"ref5","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5615-2"},{"journal-title":"Proving a computer correct in higher order logic","year":"1995","author":"joyce","key":"ref8"},{"key":"ref7","article-title":"Automatic Verification of Pipelined Microprocessor Control","volume":"818","author":"burch","year":"1994","journal-title":"International Conference on Computer-Aided Verification"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123223"},{"key":"ref1","first-page":"152","article-title":"Interfacing Fundamentals: Timing Diagram Conventions","author":"rony","year":"1980","journal-title":"Computer Design"},{"journal-title":"FMCAD'96","article-title":"Automatic Generation of Invariants in Processor Verification","year":"1996","author":"su","key":"ref9"}],"event":{"name":"ISCAS'99. 1999 IEEE International Symposium on Circuits and Systems. VLSI","acronym":"ISCAS-99","location":"Orlando, FL, USA"},"container-title":["ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6311\/16892\/00777794.pdf?arnumber=777794","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T13:25:02Z","timestamp":1497533102000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/777794\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iscas.1999.777794","relation":{},"subject":[]}}