{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T11:53:56Z","timestamp":1725450836910},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,12]]},"DOI":"10.1109\/idt.2011.6123104","type":"proceedings-article","created":{"date-parts":[[2012,1,11]],"date-time":"2012-01-11T22:00:45Z","timestamp":1326319245000},"page":"68-73","source":"Crossref","is-referenced-by-count":0,"title":["An electrical-aware parametric DFM solution for analog circuits"],"prefix":"10.1109","author":[{"given":"Rami","family":"Fathy","sequence":"first","affiliation":[]},{"given":"Ahmed","family":"Arafa","sequence":"additional","affiliation":[]},{"given":"Sherif","family":"Hany","sequence":"additional","affiliation":[]},{"given":"Abdelrahman","family":"ElMously","sequence":"additional","affiliation":[]},{"given":"Haitham","family":"Eissa","sequence":"additional","affiliation":[]},{"given":"Mohamed","family":"Dessouky","sequence":"additional","affiliation":[]},{"given":"David","family":"Nairn","sequence":"additional","affiliation":[]},{"given":"Mohab","family":"Anis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"83","article-title":"Key directions and a roadmap for electrical design for manufacturability","author":"kahng","year":"2007","journal-title":"International Solid-State Circuits Conference"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2010.5603762"},{"key":"ref12","article-title":"From poly line to transistor: Building bsim models for non-rectangular transistors","author":"poppe","year":"2006","journal-title":"SPIE"},{"key":"ref13","article-title":"Methodology of MOSFET characteristics flutuations description using BSIM3v3 SPICE model for statistical circuit siluations","author":"azuma","year":"1998","journal-title":"Int'l Workshop on Statistical Metrology Technical Papers"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1109\/ICCAD.2007.4397248","article-title":"Exploiting STI stress for performance","author":"kahng","year":"2007","journal-title":"Proc 2007 IEEE\/ACM International Conference on Computer-aided design"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320869"},{"key":"ref16","article-title":"Effect of shallow trench isolation induced stress on CMOS transistor mismatch","author":"tan","year":"2004","journal-title":"IEEE International Conference ICSE"},{"journal-title":"MOSFET Modeling and BSIM User Guide","year":"0","author":"cheng","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.44994"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2009.5397862"},{"key":"ref3","article-title":"E-DFM: The future of parametric yield success","author":"robertson","year":"0","journal-title":"Chip Design Tools Technologies and Methodologies"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2009.5404119"},{"article-title":"Effect of layout orientation on the performance and reliability of high voltage N-LDMUS in standard submicron logic STI CMOS process","year":"2005","author":"wang","key":"ref5"},{"key":"ref8","first-page":"321","article-title":"Toward a systematic-variation aware timing methodology","author":"gupta","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref7","article-title":"DFM: Where's the proof of value?","author":"kahng","year":"2006","journal-title":"DAC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041749"},{"journal-title":"Electrical-DFM Focusing on what matters to chip designers","year":"0","author":"reed","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2005.193835"}],"event":{"name":"2011 IEEE 6th International Design and Test Workshop (IDT)","start":{"date-parts":[[2011,12,11]]},"location":"Beirut, Lebanon","end":{"date-parts":[[2011,12,14]]}},"container-title":["2011 IEEE 6th International Design and Test Workshop (IDT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6111737\/6123091\/06123104.pdf?arnumber=6123104","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T12:36:56Z","timestamp":1497962216000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6123104\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/idt.2011.6123104","relation":{},"subject":[],"published":{"date-parts":[[2011,12]]}}}