{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:48:32Z","timestamp":1729662512562,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icvd.2004.1260931","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T21:52:40Z","timestamp":1087854760000},"page":"240-245","source":"Crossref","is-referenced-by-count":2,"title":["Efficient algorithms for identifying the minimum leakage states in CMOS combinational logic"],"prefix":"10.1109","author":[{"given":"K.","family":"Chopra","sequence":"first","affiliation":[]},{"given":"S.B.K.","family":"Vrudhula","sequence":"additional","affiliation":[]},{"given":"S.","family":"Bhardwaj","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968635"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606670"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2001","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.766723"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266273"},{"key":"ref15","article-title":"Edge-valued binary decision diagrams for multi-level hierarchical verification","author":"lai","year":"1992","journal-title":"Proc of DAC"},{"key":"ref16","first-page":"175","article-title":"Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage","author":"lee","year":"2003","journal-title":"Proc DAC"},{"key":"ref17","doi-asserted-by":"crossref","DOI":"10.1109\/JPROC.2002.808156","article-title":"Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicron CMOS Circuits","volume":"91","author":"roy","year":"2003","journal-title":"Proc of the IEEE"},{"key":"ref18","article-title":"CUDD: CU Decision Diagram Package, 2.3.1","author":"somenzi","year":"0","journal-title":"Dept of Elect & Comp Engg Univ of Colorado"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1023\/A:1016134730864"},{"key":"ref4","article-title":"Multi-terminal binary decision diagrams: An efficient data structure for matrix representation","author":"clarke","year":"1993","journal-title":"Proc of (IWLS)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"article-title":"Design of High-Performance Microprocessor Circuits","year":"2001","author":"chandrakasan","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LPD.1999.750412"},{"key":"ref8","article-title":"Robust SAT-Based Search Algorithm for Leakage Power Reduction","author":"fadi","year":"2002","journal-title":"Proc of PATMOS"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1990.129859"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580054"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2002.146739"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.1004317"}],"event":{"name":". 17th International Conference on VLSI Design","acronym":"ICVD-04","location":"Mumbai, India"},"container-title":["17th International Conference on VLSI Design. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8911\/28180\/01260931.pdf?arnumber=1260931","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T08:12:11Z","timestamp":1497600731000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1260931\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/icvd.2004.1260931","relation":{},"subject":[]}}