{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T20:58:38Z","timestamp":1725397118433},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006,10]]},"DOI":"10.1109\/iccd.2006.4380796","type":"proceedings-article","created":{"date-parts":[[2007,11,13]],"date-time":"2007-11-13T16:54:59Z","timestamp":1194972899000},"page":"70-75","source":"Crossref","is-referenced-by-count":2,"title":["Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects"],"prefix":"10.1109","author":[{"given":"Yasuhiro","family":"Ogasahara","sequence":"first","affiliation":[]},{"given":"Masanori","family":"Hashimoto","sequence":"additional","affiliation":[]},{"given":"Takao","family":"Onoye","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.935616"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776068"},{"article-title":"Interconnect analysis and synthesis","year":"2000","author":"cheng","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370414"},{"article-title":"Circuits, interconnections, and packaging for VLSI","year":"1990","author":"bakoglu","key":"ref14"},{"year":"2004","key":"ref15","article-title":"Raphael interconnect analysis program reference manual"},{"year":"0","key":"ref16"},{"article-title":"Digital integrated circuits a design perspecitve","year":"2003","author":"rabaey","key":"ref17"},{"year":"0","key":"ref18"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.953489"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.935616"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320924"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.395.0547"},{"year":"2005","key":"ref8","article-title":"International technology roadmap for semiconductors 2004 update interconnect"},{"year":"2005","key":"ref7","article-title":"International technology roadmap for semiconductors 2004 update process integration. devices. and structures"},{"key":"ref2","first-page":"858","article-title":"A simplified transmission-line based crosstalk noise model for on-chip RLC wiring","author":"agarwal","year":"2004","journal-title":"Proc ASP-DAC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1998.144268"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817126"}],"event":{"name":"2006 International Conference on Computer Design","start":{"date-parts":[[2007,10,1]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2007,10,4]]}},"container-title":["2006 International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4380776\/4380777\/04380796.pdf?arnumber=4380796","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T18:16:38Z","timestamp":1489688198000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4380796\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,10]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/iccd.2006.4380796","relation":{},"ISSN":["1063-6404"],"issn-type":[{"type":"print","value":"1063-6404"}],"subject":[],"published":{"date-parts":[[2006,10]]}}}