{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T21:35:51Z","timestamp":1725744951816},"reference-count":47,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,3,2]],"date-time":"2024-03-02T00:00:00Z","timestamp":1709337600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,3,2]],"date-time":"2024-03-02T00:00:00Z","timestamp":1709337600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,3,2]]},"DOI":"10.1109\/hpca57654.2024.00037","type":"proceedings-article","created":{"date-parts":[[2024,4,2]],"date-time":"2024-04-02T18:36:37Z","timestamp":1712082997000},"page":"395-408","source":"Crossref","is-referenced-by-count":0,"title":["PREFETCHX: Cross-Core Cache-Agnostic Prefetcher-based Side-Channel Attacks"],"prefix":"10.1109","author":[{"given":"Yun","family":"Chen","sequence":"first","affiliation":[{"name":"School of Computing, National University of Singapore"}]},{"given":"Ali","family":"Hajiabadi","sequence":"additional","affiliation":[{"name":"School of Computing, National University of Singapore"}]},{"given":"Lingfeng","family":"Pei","sequence":"additional","affiliation":[{"name":"School of Computing, National University of Singapore"}]},{"given":"Trevor E.","family":"Carlson","sequence":"additional","affiliation":[{"name":"School of Computing, National University of Singapore"}]}],"member":"263","reference":[{"key":"ref1","first-page":"1","article-title":"Fingerprinting at internet scale","volume-title":"Network and Distributed System Security Symposium (NDSS)","author":"P."},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2991079.2991084"},{"journal-title":"Arm Holdings plc","article-title":"MbedTLS: An open source, portable, easy to use, readable and flexible SSL library","year":"2019","key":"ref3"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2017.2654347"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00021"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3575693.3575719"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2019.8741033"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00013"},{"key":"ref10","first-page":"51","article-title":"Prime+Abort: A Timer-Free High-Precision L3 cache attack using Intel TSX","volume-title":"USENIX Security Symposium (USENIX Security","author":"Disselkoen"},{"key":"ref11","first-page":"72","article-title":"White paper inside Intel Core\u2122 microarchitecture and smart memory access","author":"Doweck","year":"2006","journal-title":"Intel Corporation"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2018.8383912"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/sp46215.2023.10179368"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2976749.2978356"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-40667-1_14"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2011.22"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00053"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/SP46214.2022.9833692"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/b978-0-12-803819-2.00018-5"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36467-6_13"},{"volume-title":"Disclosure of H\/W prefetcher control on some Intel processors","year":"2018","key":"ref22"},{"volume-title":"Intel 64 and IA-32 architectures software developers manual","year":"2019","key":"ref23"},{"volume-title":"Understanding Intel software guard extensions (Intel SGX)","year":"2021","key":"ref24"},{"volume-title":"HPC cluster tuning on 3rd generation Intel Xeon Scalable processors","year":"2022","key":"ref25"},{"volume-title":"Intel 64 and IA-32 architectures optimization reference manual","year":"2023","key":"ref26"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00002"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/SP40000.2020.00082"},{"article-title":"AMD prefetch attacks through power and time","volume-title":"USENIX Security Symposium (USENIX Security)","author":"Lipp","key":"ref29"},{"key":"ref30","first-page":"973","article-title":"Meltdown: Reading kernel memory from user space","volume-title":"D. Genkin","author":"Lipp","year":"2018"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2015.43"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/11605805_1"},{"key":"ref33","first-page":"645","article-title":"Lord of the ring(s): Side channel attacks on the CPU on-chip ring interconnect are practical","volume-title":"USENIX Security Symposium (USENIX Security)","author":"Paccagnella"},{"key":"ref34","first-page":"1","volume-title":"Cache missing for fun and profit","author":"Percival","year":"2005"},{"article-title":"Frontal Attack:\u02c7 leaking control-flow in sgx via the cpu frontend","volume-title":"USENIX Security Symposium (USENIX Security)","author":"Puddu","key":"ref35"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/EuroSPW51379.2020.00098"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3243734.3243736"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3243734.3243736"},{"key":"ref39","first-page":"1","article-title":"DNS privacy not so private: the traffic analysis perspective","volume-title":"Privacy Enhancing Technologies Symposium (PETS)","author":"Siby"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/1150019.1136508"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/SP40001.2021.00064"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/SP46214.2022.9833570"},{"key":"ref43","first-page":"1","article-title":"PAPP: Prefetcher-aware prime and probe side-channel attack","volume-title":"Design Automation Conference (DAC)","author":"Wang"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/3575693.3575700"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00004"},{"key":"ref46","first-page":"719","article-title":"Flush+Reload: A high resolution, low noise, L3 cache side-channel attack","volume-title":"USENIX Security Symposium (USENIX Security)","author":"Yarom"},{"key":"ref47","first-page":"17\u2013\u201332","article-title":"Peeping tom in the neighborhood: Keystroke eavesdropping on multi-user systems","volume-title":"USENIX Security Symposium (USENIX Security)","author":"Zhang"},{"key":"ref48","first-page":"699","article-title":"Binoculars: Contention-based side-channel attacks exploiting the page walker","volume-title":"USENIX Security Symposium (USENIX Security)","author":"Zhao"}],"event":{"name":"2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)","start":{"date-parts":[[2024,3,2]]},"location":"Edinburgh, United Kingdom","end":{"date-parts":[[2024,3,6]]}},"container-title":["2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10476359\/10476395\/10476423.pdf?arnumber=10476423","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T05:26:30Z","timestamp":1712121990000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10476423\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,3,2]]},"references-count":47,"URL":"https:\/\/doi.org\/10.1109\/hpca57654.2024.00037","relation":{},"subject":[],"published":{"date-parts":[[2024,3,2]]}}}