{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:20:41Z","timestamp":1730222441655,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,8]]},"DOI":"10.1109\/fpl.2018.00021","type":"proceedings-article","created":{"date-parts":[[2018,12,6]],"date-time":"2018-12-06T19:41:00Z","timestamp":1544125260000},"page":"76-764","source":"Crossref","is-referenced-by-count":19,"title":["DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles"],"prefix":"10.1109","author":[{"given":"Donggyu","family":"Kim","sequence":"first","affiliation":[]},{"given":"Christopher","family":"Celio","sequence":"additional","affiliation":[]},{"given":"Sagar","family":"Karandikar","sequence":"additional","affiliation":[]},{"given":"David","family":"Biancolin","sequence":"additional","affiliation":[]},{"given":"Jonathan","family":"Bachrach","sequence":"additional","affiliation":[]},{"given":"Krste","family":"Asanovic","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"1235","DOI":"10.1109\/PROC.1987.13876","article-title":"Synchronous data flow","volume":"75","author":"lee","year":"1987","journal-title":"Proceedings of the IEEE"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001151"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref13","article-title":"Evaluation of RISC-V RTL with FPGA-Accelerated Simulation","author":"kim","year":"2017","journal-title":"First Workshop on Computer Architecture Research with RISC-V (CARRV)"},{"journal-title":"Spike a RISC-V ISA Simulator","year":"2011","author":"waterman","key":"ref14"},{"key":"ref4","article-title":"Si-emulation: system verification using simulation and emulation","author":"yang","year":"2000","journal-title":"International Test Conference"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2012.87"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216950"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.46"},{"key":"ref8","article-title":"The Rocket Chip Generator","author":"asanovi?","year":"2015","journal-title":"Tech Rep UCB\/EECS-2016-17"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203780"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.102"},{"key":"ref1","article-title":"An integrated debugging environment for FPGA computing platforms","author":"camera","year":"2008","journal-title":"FPL"},{"key":"ref9","article-title":"BOOMv2: an open-source out-of-order RISC-V core","author":"celio","year":"2017","journal-title":"First Workshop on Computer Architecture Research with RISC-V (CARRV)"}],"event":{"name":"2018 28th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2018,8,27]]},"location":"Dublin, Ireland","end":{"date-parts":[[2018,8,31]]}},"container-title":["2018 28th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8529150\/8530786\/08533471.pdf?arnumber=8533471","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,12,20]],"date-time":"2018-12-20T11:03:00Z","timestamp":1545303780000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8533471\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,8]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/fpl.2018.00021","relation":{},"subject":[],"published":{"date-parts":[[2018,8]]}}}