{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T06:11:21Z","timestamp":1725516681520},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/dsd.2010.111","type":"proceedings-article","created":{"date-parts":[[2010,11,10]],"date-time":"2010-11-10T20:57:59Z","timestamp":1289422679000},"page":"805-808","source":"Crossref","is-referenced-by-count":15,"title":["Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG"],"prefix":"10.1109","author":[{"given":"Jiri","family":"Balcarek","sequence":"first","affiliation":[]},{"given":"Petr","family":"Fiser","sequence":"additional","affiliation":[]},{"given":"Jan","family":"Schmidt","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826558"},{"key":"ref11","first-page":"663","article-title":"A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan","author":"brglez","year":"1985","journal-title":"Proc of International Symposium on Circuits and Systems"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref13","first-page":"283","article-title":"Test Set Compaction Algorithms for Combinational Circuits","author":"patel","year":"1998","journal-title":"iccad International Conference on Computer-Aided Design (ICCAD '98)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766654"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041775"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915005"},{"key":"ref17","first-page":"260","article-title":"Reducing Test Application Time for Full Scan Embedded Cores","year":"1999","journal-title":"Proc of Int Symp on Fault Tolerant Computing"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923416"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1223641"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1995.470361"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/11408901_30"},{"key":"ref6","first-page":"110","article-title":"Hardware Test Pattern Generation for Built-in Testing","author":"daehn","year":"1981","journal-title":"Proc of IEEE Test Conference"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1993.470601"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2007.4295250"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ETW.2002.1029637"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-2360-5"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/43.108614"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966671"}],"event":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD)","start":{"date-parts":[[2010,9,1]]},"location":"Lille, France","end":{"date-parts":[[2010,9,3]]}},"container-title":["2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5613535\/5615428\/05615456.pdf?arnumber=5615456","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T21:07:16Z","timestamp":1489871236000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5615456\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/dsd.2010.111","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}