{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T11:13:01Z","timestamp":1725448381060},"reference-count":12,"publisher":"IEEE Comput. Soc. Press","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/dftvs.1996.572038","type":"proceedings-article","created":{"date-parts":[[2002,12,23]],"date-time":"2002-12-23T22:15:25Z","timestamp":1040681725000},"page":"310-317","source":"Crossref","is-referenced-by-count":0,"title":["Implementing fault injection and tolerance mechanisms in multiprocessor systems"],"prefix":"10.1109","author":[{"given":"D.","family":"Auder","sequence":"first","affiliation":[]},{"given":"N.","family":"Gagnon","sequence":"additional","affiliation":[]},{"given":"Y.","family":"Savaria","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1991.519504"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676773"},{"journal-title":"Methods of On-Line Error Detection and Correction in ULSI Architectures","year":"1991","author":"savaria","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1988.5306"},{"key":"ref11","first-page":"196","article-title":"Quantitative Comparisons of TMR Implementations in a Multiprocessor System","author":"audet","year":"1996","journal-title":"Proc On-Line Testing Workshop"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1989.105592"},{"journal-title":"PSC\/2 and iPSC\/860 User s Guide","year":"1989","key":"ref12"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1992.243567"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.54853"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1989.105590"},{"journal-title":"Parallel Microprocessor Architecture","year":"1994","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/2.386985"}],"event":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","acronym":"DFTVS-96","location":"Boston, MA, USA"},"container-title":["Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx3\/4201\/12360\/00572038.pdf?arnumber=572038","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,9]],"date-time":"2017-03-09T19:05:21Z","timestamp":1489086321000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/572038\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/dftvs.1996.572038","relation":{},"subject":[]}}