{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T15:11:00Z","timestamp":1730214660404,"version":"3.28.0"},"reference-count":33,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1995]]},"DOI":"10.1109\/dftvs.1995.476932","type":"proceedings-article","created":{"date-parts":[[2002,11,19]],"date-time":"2002-11-19T17:10:21Z","timestamp":1037725821000},"page":"10-18","source":"Crossref","is-referenced-by-count":9,"title":["AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout"],"prefix":"10.1109","author":[{"given":"I.","family":"Bubel","sequence":"first","affiliation":[{"name":"Fraunhofer-Inst. fur Festkorpertechnologie, Munich, Germany"}]},{"given":"W.","family":"Maly","sequence":"additional","affiliation":[]},{"given":"T.","family":"Waas","sequence":"additional","affiliation":[]},{"given":"P.K.","family":"Nag","sequence":"additional","affiliation":[]},{"given":"H.","family":"Hartmann","sequence":"additional","affiliation":[]},{"given":"D.","family":"Schmitt-Landsiedel","sequence":"additional","affiliation":[]},{"given":"S.","family":"Griep","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1991.199943"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1991.164130"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICMTS.1993.292890"},{"journal-title":"aiss GmbH","year":"1989","author":"waas","key":"ref30"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/66.382281"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/66.382282"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050474"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1147\/rd.284.0461"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1147\/rd.276.0549"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/66.56568"},{"key":"ref16","first-page":"148","article-title":"Yield Model for Manufacturing Strategy Planning and Product Shrink Applications","author":"maly","year":"94","journal-title":"Semiconductor International"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1986.1270225"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/66.382278"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1049\/el:19830156"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/66.382276"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/66.149812"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1993.595763"},{"key":"ref3","article-title":"Yield Diagnosis Through Interpretation of Tester Data","author":"maly","year":"1987","journal-title":"Proc of ITC 87"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/66.388016"},{"journal-title":"Atlas of IC Technologies An Introduction to VLSI Processes","year":"1987","author":"maly","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-6799-8_11"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/66.85945"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.240078"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/5.52217"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/EURDAC.1992.246215"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"135","DOI":"10.1145\/196244.196311","article-title":"cost of silicon viewed from vlsi design perspective","author":"maly","year":"1994","journal-title":"31st Design Automation Conference"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1985.1270112"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"1727","DOI":"10.1109\/T-ED.1985.22187","article-title":"role of defect size distribution in yield modeling","volume":"32","author":"ferris-prabhu","year":"1985","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1985.1052403"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICWSI.1992.171820"},{"key":"ref23","first-page":"267","article-title":"Yield Estimation of VLSI Circuits","author":"nag","year":"1990","journal-title":"Proceedings of TECHCON 90"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/4.192046"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/43.127625"}],"event":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","start":{"date-parts":[[1995,11,13]]},"location":"Lafayette, LA, USA","end":{"date-parts":[[1995,11,15]]}},"container-title":["Proceedings of International Workshop on Defect and Fault Tolerance in VLSI"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx2\/3462\/10208\/00476932.pdf?arnumber=476932","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,7]],"date-time":"2021-06-07T17:08:42Z","timestamp":1623085722000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/476932\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/dftvs.1995.476932","relation":{},"subject":[],"published":{"date-parts":[[1995]]}}}