{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T14:53:47Z","timestamp":1730213627921,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/dasip48288.2019.9049195","type":"proceedings-article","created":{"date-parts":[[2020,3,31]],"date-time":"2020-03-31T04:44:39Z","timestamp":1585629879000},"page":"35-40","source":"Crossref","is-referenced-by-count":4,"title":["Hybrid Prototyping Methodology for Rapid System Validation in HW\/SW Co-Design"],"prefix":"10.1109","author":[{"given":"Arief","family":"Wicaksana","sequence":"first","affiliation":[]},{"given":"Amir","family":"Charif","sequence":"additional","affiliation":[]},{"given":"Caaliph","family":"Andriamisaina","sequence":"additional","affiliation":[]},{"given":"Nicolas","family":"Ventroux","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Integrated Logic Analyzer (ILA)","year":"0","key":"ref10"},{"journal-title":"Signaltap ii logic analyzer","year":"0","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/APASIC.2004.1349442"},{"key":"ref13","first-page":"123","article-title":"FPGA-based platform for fast accurate evaluation of Ultra Low Power SoC","author":"guillaume","year":"2018","journal-title":"2018 28th International Symposium on Power and Timing Modeling Optimization and Simulation (PATMOS)"},{"key":"ref14","article-title":"Plug&Chip: A Framework for Supporting Rapid Prototyping of 3D Hybrid Virtual SoCs","volume":"13","author":"dionysios","year":"2014","journal-title":"ACM Trans Embedded Comput Syst (TECS)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2015.7517196"},{"journal-title":"HAPS Prototyping Solutions","year":"0","key":"ref16"},{"journal-title":"ProFPGA duo Motherboard","year":"0","key":"ref17"},{"key":"ref18","first-page":"1039","article-title":"PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks","author":"alexandre","year":"2018","journal-title":"2018 Design Automation & Test in Europe Conference & Exhibition (DATE)"},{"journal-title":"Questa Advanced Simulator","year":"0","key":"ref19"},{"key":"ref4","article-title":"OSCI TLM-2.0 Language Reference Manual","volume":"24","author":"john","year":"2009","journal-title":"Open SystemC Initiative"},{"key":"ref3","first-page":"39","article-title":"Embracing the FPGA Challenge for Processor Design Verification","author":"nitin","year":"2014","journal-title":"2014 15th International Microprocessor Test and Verification Workshop"},{"key":"ref6","first-page":"2338","article-title":"Mixed SW\/SystemC SoC Emulation Framework","author":"marius","year":"2007","journal-title":"Industrial Electronics 2007 ISIE 2007 IEEE International Symposium"},{"key":"ref5","first-page":"125","article-title":"A HW\/SW Co-simulation Framework for the Verification of Multi-CPU Systems","author":"stefano","year":"2008","journal-title":"High Level Design Validation and Test Workshop 2008 HLDVT '08 IEEE International"},{"key":"ref8","first-page":"299","article-title":"A Fast Hardware\/Software Co-verification Method for System-on-a-Chip by using a C\/C++ Simulator and FPGA Emulator with Shared Register Communication","author":"yuichi","year":"2004","journal-title":"Proceedings of the 41st Annual Design Automation Conference"},{"key":"ref7","doi-asserted-by":"crossref","DOI":"10.1145\/3300189.3300192","article-title":"Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration","author":"amir charif","year":"2019","journal-title":"Proc the Workshop on Rapid Simulation and Performance Evaluation Methods and Tools"},{"key":"ref2","first-page":"439","article-title":"Hardware\/Software Co-simulation","author":"james","year":"1994","journal-title":"31st Design Automation Conference"},{"journal-title":"Handbook of Hardware\/Software Codesign","year":"2017","author":"soonhoi","key":"ref1"},{"key":"ref9","first-page":"747","article-title":"An SoC Design Methodology using FPGAs and Embedded Microprocessors","author":"nobuyuki","year":"2004","journal-title":"Proceedings of the 41st Annual Design Automation Conference"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCAS.2010.5581847"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1145\/1147224.1147225","article-title":"Statistical Sampling of Microarchitecture Simulation","volume":"16","author":"roland","year":"2006","journal-title":"ACM Transactions on Modeling and Computer Simulation (TOMACS)"}],"event":{"name":"2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)","start":{"date-parts":[[2019,10,16]]},"location":"Montreal, QC, Canada","end":{"date-parts":[[2019,10,18]]}},"container-title":["2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9035666\/9049168\/09049195.pdf?arnumber=9049195","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T20:26:16Z","timestamp":1658262376000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9049195\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/dasip48288.2019.9049195","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}