{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T03:12:22Z","timestamp":1725678742917},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,5]]},"DOI":"10.1109\/async.2012.29","type":"proceedings-article","created":{"date-parts":[[2012,7,31]],"date-time":"2012-07-31T16:38:32Z","timestamp":1343752712000},"page":"73-80","source":"Crossref","is-referenced-by-count":24,"title":["A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits"],"prefix":"10.1109","author":[{"given":"Yvain","family":"Thonnart","sequence":"first","affiliation":[]},{"given":"Edith","family":"Beigne","sequence":"additional","affiliation":[]},{"given":"Pascal","family":"Vivet","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Synthesis of Quasi-Delay-Insensitive Datapath Circuits","year":"2006","author":"toms","key":"19"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.114"},{"journal-title":"Pipelined Asynchronous Circuits","year":"1995","author":"lines","key":"18"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2011.13"},{"journal-title":"Library Characterization and Static Timing Analysis of Template Based Asynchronous Circuits","year":"2007","author":"prakash","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1018139"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2009.31"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228858"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2000.836983"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2005.22"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457239"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/43.980253"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/5.740025"},{"key":"10","article-title":"Designing fast asynchronous circuits","author":"sutherland","year":"0","journal-title":"Proc Intl Symp on Asynchronous Circuits and Systems ASYNC 2001"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/WCADM.1995.514647"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4612-4476-9_35"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763222"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2009.5413183"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2009.27"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2001.913347"}],"event":{"name":"2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","start":{"date-parts":[[2012,5,7]]},"location":"Kgs. Lyngby, Denmark","end":{"date-parts":[[2012,5,9]]}},"container-title":["2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6242773\/6243861\/06243884.pdf?arnumber=6243884","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T19:24:53Z","timestamp":1490124293000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6243884\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/async.2012.29","relation":{},"subject":[],"published":{"date-parts":[[2012,5]]}}}