{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,4,11]],"date-time":"2024-04-11T05:53:00Z","timestamp":1712814780435},"reference-count":61,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100000923","name":"Australian Research Council","doi-asserted-by":"publisher","award":["DP180104188"],"id":[{"id":"10.13039\/501100000923","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2021]]},"DOI":"10.1109\/access.2021.3100618","type":"journal-article","created":{"date-parts":[[2021,7,27]],"date-time":"2021-07-27T20:27:02Z","timestamp":1627417622000},"page":"108411-108425","source":"Crossref","is-referenced-by-count":5,"title":["UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks"],"prefix":"10.1109","volume":"9","author":[{"ORCID":"http:\/\/orcid.org\/0000-0003-1910-4048","authenticated-orcid":false,"given":"Darshana","family":"Jayasinghe","sequence":"first","affiliation":[]},{"ORCID":"http:\/\/orcid.org\/0000-0001-7427-4934","authenticated-orcid":false,"given":"Aleksandar","family":"Ignjatovic","sequence":"additional","affiliation":[]},{"given":"Sri","family":"Parameswaran","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ICCITechn.2012.6509803"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/RTC.2012.6418105"},{"key":"ref33","author":"tatsukawa","year":"2017","journal-title":"MMCM and PLL Dynamic Reconfiguration"},{"key":"ref32","article-title":"Obfuscating against side-channel power analysis using hiding techniques for AES","author":"fritzke","year":"2012"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465395"},{"key":"ref30","first-page":"201","article-title":"FPGA implementation and analysis of random delay insertion countermeasure against DPA","author":"lu","year":"2008","journal-title":"Proc Int Conf Field-Program Technol"},{"key":"ref37","year":"2015","journal-title":"Cost-optimized portfolio product tables and product selection guide"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2019.8885394"},{"key":"ref35","first-page":"1090","author":"kirch","year":"2008","journal-title":"Pearson Correlation Coefficient"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2009.40"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2802867"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2018.00118"},{"key":"ref27","first-page":"33","article-title":"Generic side-channel countermeasures for reconfigurable devices","author":"g\u00fcneysu","year":"2011","journal-title":"Proc CHES"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-15031-9_7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.comnet.2020.107593"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714904"},{"key":"ref22","year":"2021","journal-title":"Amazon EC2 F1 instances"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00029"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942094"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116481"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942112"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317899"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.61"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-21476-4_6"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1145\/1857927.1857938"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/INNOVATIONS.2012.6207713"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176671"},{"key":"ref56","first-page":"236","article-title":"Combinational logic design for AES subbyte transformation on masked data","volume":"2003","author":"trichina","year":"2003","journal-title":"IACR Cryptol ePrint Arch"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2017.25"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2015.7324539"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_13"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/1502781.1502784"},{"key":"ref10","first-page":"17","article-title":"Investigations of power analysis attacks on smartcards","author":"messerges","year":"1999","journal-title":"Proc USENIX Workshop Smartcard Technol (WOST)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-018-0032-7"},{"key":"ref40","year":"2018","journal-title":"7 Series FPGAs SelectIO Resources User Guide"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"35","DOI":"10.1007\/978-3-540-45238-6_4","article-title":"Power-analysis attacks on an FPGA—First experimental results","author":"\u00f6rs","year":"2003","journal-title":"Cryptographic Hardware and Embedded Systems - CHES 2003"},{"key":"ref13","author":"mangard","year":"2007","journal-title":"Power Analysis Attacks Revealing the Secrets of Smart Cards"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342177"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435283"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig48160.2019.8994789"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3340557"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i3.121-146"},{"key":"ref19","article-title":"Cryptographically secure multi-tenant provisioning of FPGAs","author":"bag","year":"2018","journal-title":"arXiv 1802 04136"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-68697-5_9"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36400-5_4"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3394885.3431638"},{"key":"ref5","article-title":"Cache-timing attacks on AES","author":"bernstein","year":"2005"},{"key":"ref8","author":"hankerson","year":"2003","journal-title":"Guide to Elliptic Curve Cryptography"},{"key":"ref7","article-title":"Federal information processing standards publication 197 announcing the advanced encryption standard (AES)","year":"2001"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_26"},{"key":"ref9","first-page":"546","article-title":"Power-analysis attack on an ASIC AES implementation","volume":"2","author":"\u00f6rs","year":"2004","journal-title":"Proc Int Conf Inf Technol Coding Comput (ITCC)"},{"key":"ref46","first-page":"193","article-title":"Sliding-window correlation attacks against encryption devices with an unstable clock","author":"fledel","year":"2018","journal-title":"Proc 25th Int Conf Sel Areas Cryptogr"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-40349-1_2"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974678"},{"key":"ref47","first-page":"536","article-title":"Principal component analysis and side-channel attacks","author":"batina","year":"2010"},{"key":"ref42","year":"2016","journal-title":"iCE40 sysCLOCK PLL Design and Usage Guide"},{"key":"ref41","year":"2016","journal-title":"LogiCORE IP Utility IDELAYCTRL Logic (V1 0)"},{"key":"ref44","article-title":"Software-based fault and power side-channel attacks inside multi-tenant FPGAs","author":"krautter","year":"2019","journal-title":"Proc Demo Session IEEE Int Symp Hardw Oriented Secur Trust (HOST)"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/GCCE.2012.6379944"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/9312710\/09499089.pdf?arnumber=9499089","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:57:15Z","timestamp":1639771035000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9499089\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"references-count":61,"URL":"https:\/\/doi.org\/10.1109\/access.2021.3100618","relation":{},"ISSN":["2169-3536"],"issn-type":[{"value":"2169-3536","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021]]}}}